Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

RADDHN2 (8H)

Test 1: uops

Code:

  raddhn2 v0.16b, v1.8h, v2.8h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000

Test 2: Latency 1->1

Code:

  raddhn2 v0.16b, v1.8h, v2.8h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 3: Latency 1->2

Code:

  raddhn2 v0.16b, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620030018110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 4: Latency 1->3

Code:

  raddhn2 v0.16b, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204300331010110110000010010000300768905101002001000620030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000620030018110000100
10204300331010110110000010010000300768905101002001000420030018110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  raddhn2 v0.16b, v8.8h, v9.8h
  movi v1.16b, 0
  raddhn2 v1.16b, v8.8h, v9.8h
  movi v2.16b, 0
  raddhn2 v2.16b, v8.8h, v9.8h
  movi v3.16b, 0
  raddhn2 v3.16b, v8.8h, v9.8h
  movi v4.16b, 0
  raddhn2 v4.16b, v8.8h, v9.8h
  movi v5.16b, 0
  raddhn2 v5.16b, v8.8h, v9.8h
  movi v6.16b, 0
  raddhn2 v6.16b, v8.8h, v9.8h
  movi v7.16b, 0
  raddhn2 v7.16b, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044051680109101800081008001230032005680113200800132002400391160000100
1602044010780109101800081008001230032005280112200800122002400361160000100
1602044011080110101800091008001330032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5054

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244380580020118000910800133032000080010208000020240000116000010
1600244125280011118000010800003032000080010208000020240000116000010
1600244043180011118000010800003032000080010208000020240000116000010
1600244038980011118000010800003032000080010208000020240000116000010
1600244040780011118000010800003032000080010208000020240147116000010
1600244071880011118000010800003032000080010208000020240000116000010
1600244040880011118000010800003032000080010208000020240000116000010
1600244044680011118000010800003032000080010208000020240000116000010
1600244044980011118000010800003032000080010208000020240000116000010
1600244040880011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  raddhn2 v0.16b, v16.8h, v17.8h
  raddhn2 v1.16b, v16.8h, v17.8h
  raddhn2 v2.16b, v16.8h, v17.8h
  raddhn2 v3.16b, v16.8h, v17.8h
  raddhn2 v4.16b, v16.8h, v17.8h
  raddhn2 v5.16b, v16.8h, v17.8h
  raddhn2 v6.16b, v16.8h, v17.8h
  raddhn2 v7.16b, v16.8h, v17.8h
  raddhn2 v8.16b, v16.8h, v17.8h
  raddhn2 v9.16b, v16.8h, v17.8h
  raddhn2 v10.16b, v16.8h, v17.8h
  raddhn2 v11.16b, v16.8h, v17.8h
  raddhn2 v12.16b, v16.8h, v17.8h
  raddhn2 v13.16b, v16.8h, v17.8h
  raddhn2 v14.16b, v16.8h, v17.8h
  raddhn2 v15.16b, v16.8h, v17.8h
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204801111601071011600061001600103006400441601102001600142004800421160000100
160204800451601071011600061001600103006400441601102001600132004801921160000100
160204800451601071011600061001600103006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601071011600061001600103006400361601082001600122004800361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600248017216001711160006010160010306400521600222016001520480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600258007116005311160042010160054306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600258007116005311160042010160054306400001600102016000020480000116000010