Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

REV64 (vector, 8H)

Test 1: uops

Code:

  rev64 v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000
1004203310011100010005024810001000100011000

Test 2: Latency 1->2

Code:

  rev64 v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
102042003310101101100001001000030050924810100200100062000100061010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100
102042003310101101100001001000030750948810136202100462000100041010000100
102042003310101101100001001000030050924810100200100042000100041010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092471002020100062010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010
10024200331002121100002010000705092481002020100002010000111000010

Test 3: throughput

Count: 8

Code:

  rev64 v0.8h, v8.8h
  rev64 v1.8h, v8.8h
  rev64 v2.8h, v8.8h
  rev64 v3.8h, v8.8h
  rev64 v4.8h, v8.8h
  rev64 v5.8h, v8.8h
  rev64 v6.8h, v8.8h
  rev64 v7.8h, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
8020440064801071018000610080010300320036801082008001220080014180000100
8020440044801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320036801082008001220080012180000100
8020440034801051018000410080008300320208801542008006320080014180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80024401278002721800062080010703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080064118000010
80024400348002121800002080000703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080000118000010
80024400348002121800002080000703200008002020800002080000118000010