Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SABAL2 (vector, 4S)

Test 1: uops

Code:

  sabal2 v0.4s, v1.8h, v2.8h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000

Test 2: Latency 1->1

Code:

  sabal2 v0.4s, v1.8h, v2.8h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
102043003310101101100001001000030076887910100200100042000300121010000100
102043003310101101100001001000031477108910236204101662000301321010000100
102043003310101101100001001000030076890510100200100042000300121010000100
102043003310101101100001001000030076890510100200100042000300121010000100
102043003310101101100001001000030076890510100200100042000300121010000100
102043003310101101100001001000030076890510100200100042000300121010000100
102043003310101101100001001000030076890510100200100042000300121010000100
102043003310101101100001001000031476991210170204100842020302462010000100
102043003310101101100001001000030076890510100200100042000300121010000100
102043003310101101100001001000030076890510100200100042000300121010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10025300661002721100062010031707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 3: Latency 1->2

Code:

  sabal2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620030018110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100243013510037211001602010066707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000757710891015422101612030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010

Test 4: Latency 1->3

Code:

  sabal2 v0.4s, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204300331010110110000010010000030007689051010020001000420030018110000100
10204300331010110110000010010000030007689051010020001000420030012110000100
10204300331010110110000010010000030007689051010020001000420030012110000100
10204300331010110110000010010000030007689051010020001000420030012110000100
10204300331010110110000010010000030007689051010020001000420030012110000100
10204300331010110110000010010000030007689051010020001000420030012110000100
10204300331010110110000010010000030007689051010020001000420030012110000100
10204300331010110110000010010000030007689051010020001000420030012110000100
10204300331010110110000010010000030007689051010020001000420030012110000100
10204300331010110110000010010000030007689051010020001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sabal2 v0.4s, v8.8h, v9.8h
  movi v1.16b, 0
  sabal2 v1.4s, v8.8h, v9.8h
  movi v2.16b, 0
  sabal2 v2.4s, v8.8h, v9.8h
  movi v3.16b, 0
  sabal2 v3.4s, v8.8h, v9.8h
  movi v4.16b, 0
  sabal2 v4.4s, v8.8h, v9.8h
  movi v5.16b, 0
  sabal2 v5.4s, v8.8h, v9.8h
  movi v6.16b, 0
  sabal2 v6.4s, v8.8h, v9.8h
  movi v7.16b, 0
  sabal2 v7.4s, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
16020440500801091018000801008001230032005680113200800132002400391160000100
16020540170801441018004301008004730032005680113200800132002400391160000100
16020440086801091018000801008001230032005280112200800122002400361160000100
16020440086801091018000801008001230032005280112200800122002401471160000100
16020440096801091018000801008001230032005280112200800122002400361160000100
16020440086801091018000801008001230032005280112200800122002400361160000100
16020440086801091018000801008001230032005280112200800122002400361160000100
16020440086801091018000801008001230032005280112200800122002400361160000100
16020440086801091018000801008001230032005280112200800122002400361160000100
16020440086801091018000801008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244385280020118000910800133032000080010208000020240000116000010
1600244128180011118000010800003032000080010208000020240000116000010
1600244042780011118000010800003032000080010208000020240000116000010
1600244041880011118000010800003032000080010208000020240000116000010
1600244038080011118000010800003032000080010208000020240000116000010
1600244043080011118000010800003032000080010208000020240000116000010
1600244038580011118000010800003032000080010208000020240000116000010
1600254050780053118004210800463032000080010208000020240000116000010
1600244044380011118000010800003032000080010208000020240000116000010
1600244043580011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  sabal2 v0.4s, v16.8h, v17.8h
  sabal2 v1.4s, v16.8h, v17.8h
  sabal2 v2.4s, v16.8h, v17.8h
  sabal2 v3.4s, v16.8h, v17.8h
  sabal2 v4.4s, v16.8h, v17.8h
  sabal2 v5.4s, v16.8h, v17.8h
  sabal2 v6.4s, v16.8h, v17.8h
  sabal2 v7.4s, v16.8h, v17.8h
  sabal2 v8.4s, v16.8h, v17.8h
  sabal2 v9.4s, v16.8h, v17.8h
  sabal2 v10.4s, v16.8h, v17.8h
  sabal2 v11.4s, v16.8h, v17.8h
  sabal2 v12.4s, v16.8h, v17.8h
  sabal2 v13.4s, v16.8h, v17.8h
  sabal2 v14.4s, v16.8h, v17.8h
  sabal2 v15.4s, v16.8h, v17.8h
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800591601051011600041001600080300064004416011020001600132004800391160000100
160204800351601071011600061001600100300064003616010820001600122004800361160000100
160204800351601071011600061001600100300064003616010820001600122004800361160000100
160204800351601051011600041001600080300064003616010820001600122004800361160000100
160204800351601071011600061001600100300064003616010820001600122004800361160000100
160204800351601051011600041001600080300064003616010820001600122004800361160000100
160204800351601071011600061001600100300064021616015620001600642004800361160000100
160204800351601051011600041001600080300064003616010820001600122004800361160000100
160204800351601051011600041001600080300064020816015420001600632004800361160000100
160204800351601051011600041001600080300064003616010820001600122004800361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600248018316001811160007010160011306400001600102016000020480000116000010
1600248005216001111160000010160000306400001600102016000020480000116000010
1600248014316001111160000010160000306400001600102016000020480294116000010
1600248033316020811160197010160197306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306402161600662016006320480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010