Icestorm: SABAL2 (vector, 4S) measurements

Code:

  sabal2 v0.4s, v1.8h, v2.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  sabal2 v0.4s, v1.8h, v2.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768879	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	314	771089	10236	204	10166	200	0	30132	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	314	769912	10170	204	10084	202	0	30246	2	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10025	30066	10027	21	10006	20	10031	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  sabal2 v0.4s, v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	30018	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30135	10037	21	10016	0	20	10066	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	75	771089	10154	22	10161	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  sabal2 v0.4s, v1.8h, v0.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	0	100	10000	0	300	0	768905	10100	200	0	10004	200	30018	1	10000	100
10204	30033	10101	101	10000	0	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	0	300	0	768905	10100	200	0	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sabal2 v0.4s, v8.8h, v9.8h
  movi v1.16b, 0
  sabal2 v1.4s, v8.8h, v9.8h
  movi v2.16b, 0
  sabal2 v2.4s, v8.8h, v9.8h
  movi v3.16b, 0
  sabal2 v3.4s, v8.8h, v9.8h
  movi v4.16b, 0
  sabal2 v4.4s, v8.8h, v9.8h
  movi v5.16b, 0
  sabal2 v5.4s, v8.8h, v9.8h
  movi v6.16b, 0
  sabal2 v6.4s, v8.8h, v9.8h
  movi v7.16b, 0
  sabal2 v7.4s, v8.8h, v9.8h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40500	80109	101	80008	0	100	80012	300	320056	80113	200	80013	200	240039	1	160000	100
160205	40170	80144	101	80043	0	100	80047	300	320056	80113	200	80013	200	240039	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	240147	1	160000	100
160204	40096	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43852	80020	11	80009	10	80013	30	320000	80010	20	80000	20	240000	1	160000	10
160024	41281	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40427	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40418	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40380	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40430	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40385	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160025	40507	80053	11	80042	10	80046	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40443	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40435	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 16

Code:

  sabal2 v0.4s, v16.8h, v17.8h
  sabal2 v1.4s, v16.8h, v17.8h
  sabal2 v2.4s, v16.8h, v17.8h
  sabal2 v3.4s, v16.8h, v17.8h
  sabal2 v4.4s, v16.8h, v17.8h
  sabal2 v5.4s, v16.8h, v17.8h
  sabal2 v6.4s, v16.8h, v17.8h
  sabal2 v7.4s, v16.8h, v17.8h
  sabal2 v8.4s, v16.8h, v17.8h
  sabal2 v9.4s, v16.8h, v17.8h
  sabal2 v10.4s, v16.8h, v17.8h
  sabal2 v11.4s, v16.8h, v17.8h
  sabal2 v12.4s, v16.8h, v17.8h
  sabal2 v13.4s, v16.8h, v17.8h
  sabal2 v14.4s, v16.8h, v17.8h
  sabal2 v15.4s, v16.8h, v17.8h

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80059	160105	101	160004	100	160008	0	300	0	640044	160110	200	0	160013	200	480039	1	160000	100
160204	80035	160107	101	160006	100	160010	0	300	0	640036	160108	200	0	160012	200	480036	1	160000	100
160204	80035	160107	101	160006	100	160010	0	300	0	640036	160108	200	0	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	480036	1	160000	100
160204	80035	160107	101	160006	100	160010	0	300	0	640036	160108	200	0	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	480036	1	160000	100
160204	80035	160107	101	160006	100	160010	0	300	0	640216	160156	200	0	160064	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640208	160154	200	0	160063	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	480036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80183	160018	11	160007	0	10	160011	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80052	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80143	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480294	1	160000	10
160024	80333	160208	11	160197	0	10	160197	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640216	160066	20	160063	20	480000	1	160000	10
160024	80035	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10

SABAL2 (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations