Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SABA (vector, 8B)

Test 1: uops

Code:

  saba v0.8b, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000

Test 2: Latency 1->1

Code:

  saba v0.8b, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 3: Latency 1->2

Code:

  saba v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300769247101312001004420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 4: Latency 1->3

Code:

  saba v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1020430033101011011000001001000030076890510100200100062000300181010000100
1845549580174155188816940585014820730076890510100200100062000300181010000100
1020430033101011011000001001000030076890510100200100062000300121010000100
1020430033101011011000001001000030076890510100200100042000300121010000100
1020430033101011011000001001000030076890510100200100042000300121010000100
1020430033101011011000001001000030076890510100200100042000300121010000100
1020430033101011011000001001000030076890510100200100042000300121010000100
1020430033101011011000001001000030076890510100200100042000300121010000100
1020430033101011011000001001000030076890510100200100042000300121010000100
1020430033101011011000001001000030076890510100200100042000300121010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030123111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030012111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  saba v0.8b, v8.8b, v9.8b
  movi v1.16b, 0
  saba v1.8b, v8.8b, v9.8b
  movi v2.16b, 0
  saba v2.8b, v8.8b, v9.8b
  movi v3.16b, 0
  saba v3.8b, v8.8b, v9.8b
  movi v4.16b, 0
  saba v4.8b, v8.8b, v9.8b
  movi v5.16b, 0
  saba v5.8b, v8.8b, v9.8b
  movi v6.16b, 0
  saba v6.8b, v8.8b, v9.8b
  movi v7.16b, 0
  saba v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
160204404898010910180008100800123003200528011220080012200024003910160000100
160204401218010910180008100800123003200528011220080012200024003910160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100
160204400868010910180008100800123003200528011220080012200024003610160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
160024438228002011800091080013303200008001020800002002400001016000010
160024412848001111800001080000303200008001020800002002400001016000010
160024414808001111800001080000303200008001020800002002400001016000010
160024403668001111800001080000303200008001020800002002400001016000010
160024404188001111800001080000303200008001020800002002400001016000010
160024404018001111800001080000303200008001020800002002400001016000010
160024404168001111800001080000303200008001020800002002400001016000010
160024405168001111800001080000303200008001020800002002400001016000010
160024404108001111800001080000303200008001020800002002400001016000010
160024404088001111800001080000303200008001020800002002400001016000010

Test 6: throughput

Count: 16

Code:

  saba v0.8b, v16.8b, v17.8b
  saba v1.8b, v16.8b, v17.8b
  saba v2.8b, v16.8b, v17.8b
  saba v3.8b, v16.8b, v17.8b
  saba v4.8b, v16.8b, v17.8b
  saba v5.8b, v16.8b, v17.8b
  saba v6.8b, v16.8b, v17.8b
  saba v7.8b, v16.8b, v17.8b
  saba v8.8b, v16.8b, v17.8b
  saba v9.8b, v16.8b, v17.8b
  saba v10.8b, v16.8b, v17.8b
  saba v11.8b, v16.8b, v17.8b
  saba v12.8b, v16.8b, v17.8b
  saba v13.8b, v16.8b, v17.8b
  saba v14.8b, v16.8b, v17.8b
  saba v15.8b, v16.8b, v17.8b
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602048017216010710116000601001600103006400441601102001600142004800421160000100
1602048003516010710116000601001600103006402161601562001600642004800361160000100
1602048003616010710116000601001600103006400361601082001600122004800361160000100
126496109372125100146911023668043147001023693006400361601082001600122004800391160000100
1602048003516010510116000401001600083006400361601082001600122004800361160000100
1602048003516010510116000401001600083006400361601082001600122004800361160000100
1602048003516010710116000601001600103006400361601082001600122004800361160000100
1602048003516010510116000401001600083006400361601082001600122004800361160000100
1602048003516010510116000401001600083006400361601082001600122004800361160000100
1602048003516010510116000401001600083006400361601082001600122004800361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600248016716001511160004010160008306400441600202016001420480000116000010
1600248003616001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010