Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SADALP (vector, 1D)

Test 1: uops

Code:

  sadalp v0.1d, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->1

Code:

  sadalp v0.1d, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620020012110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020530066101071011000610010031300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100062020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010

Test 3: Latency 1->2

Code:

  sadalp v0.1d, v0.2s
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020008111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020012111000010
10024300331002121100002010000707689051002020100042020008111000010
10024300331002121100002010000707689051002020100042020008111000010
10024300331002121100002010000707689051002020100042020008111000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sadalp v0.1d, v8.2s
  movi v1.16b, 0
  sadalp v1.1d, v8.2s
  movi v2.16b, 0
  sadalp v2.1d, v8.2s
  movi v3.16b, 0
  sadalp v3.1d, v8.2s
  movi v4.16b, 0
  sadalp v4.1d, v8.2s
  movi v5.16b, 0
  sadalp v5.1d, v8.2s
  movi v6.16b, 0
  sadalp v6.1d, v8.2s
  movi v7.16b, 0
  sadalp v7.1d, v8.2s
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044048980109101800081008001230032005280112200800122001600241160000100
1602044012180110101800091008001330032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001601001160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244378780019118000810800123032000080010208000020160000116000010
1600244123880011118000010800003032000080010208000020160000116000010
1600244043580011118000010800003032000080010208000020160000116000010
1600244043080011118000010800003032000080010208000020160000116000010
1600244042680011118000010800003032000080010208000020160000116000010
1600244042680011118000010800003032000080010208000020160000116000010
1600244043880011118000010800003032000080010208000020160000116000010
1600244038780011118000010800003032000080010208000020160000116000010
1600244041780011118000010800003032000080010208000020160000116000010
1600244042580011118000010800003032000080010208000020160000116000010

Test 5: throughput

Count: 16

Code:

  sadalp v0.1d, v16.2s
  sadalp v1.1d, v16.2s
  sadalp v2.1d, v16.2s
  sadalp v3.1d, v16.2s
  sadalp v4.1d, v16.2s
  sadalp v5.1d, v16.2s
  sadalp v6.1d, v16.2s
  sadalp v7.1d, v16.2s
  sadalp v8.1d, v16.2s
  sadalp v9.1d, v16.2s
  sadalp v10.1d, v16.2s
  sadalp v11.1d, v16.2s
  sadalp v12.1d, v16.2s
  sadalp v13.1d, v16.2s
  sadalp v14.1d, v16.2s
  sadalp v15.1d, v16.2s
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800581601051011600041001600083006400361601082001600122003200281160000100
160204800451601051011600041001600083006400361601082001600122003200281160000100
160204800611601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200281160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003201301160000100
160204800351601071011600061001600103006400361601082001600122003200241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024802011600171116000610160010306400441600202016001420320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160025800701600531116004210160054306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160025800781600521116004110160053306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010