Icestorm: SADALP (vector, 2D) measurements

Code:

  sadalp v0.2d, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  sadalp v0.2d, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	20012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0137

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	66	769451	10053	20	10039	20	20076	11	10000	10
10024	30085	10029	21	10008	20	10033	70	769451	10053	20	10040	20	20078	11	10000	10
10024	30137	10037	21	10016	20	10066	70	769451	10053	20	10038	20	20078	11	10000	10
10024	30083	10029	21	10008	20	10033	70	769451	10053	20	10038	20	20158	11	10000	10
10024	30135	10037	21	10016	20	10066	68	769451	10053	20	10040	20	20164	11	10000	10
10024	30187	10045	21	10024	20	10099	67	770543	10119	20	10120	20	20244	11	10000	10
10025	30220	10051	21	10030	20	10130	70	769997	10086	20	10078	20	20242	11	10000	10
10024	30238	10055	23	10032	22	10132	64	770543	10119	20	10117	20	20240	11	10000	10
10024	30186	10045	21	10024	20	10099	69	770543	10119	20	10115	20	20324	11	10000	10
10024	30237	10053	21	10032	20	10132	67	770543	10119	20	10117	20	20240	11	10000	10

Test 3: Latency 1->2

Code:

  sadalp v0.2d, v0.4s

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	68	771089	10152	20	10161	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20080	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20170	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30084	10029	21	10008	20	10033	70	768905	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sadalp v0.2d, v8.4s
  movi v1.16b, 0
  sadalp v1.2d, v8.4s
  movi v2.16b, 0
  sadalp v2.2d, v8.4s
  movi v3.16b, 0
  sadalp v3.2d, v8.4s
  movi v4.16b, 0
  sadalp v4.2d, v8.4s
  movi v5.16b, 0
  sadalp v5.2d, v8.4s
  movi v6.16b, 0
  sadalp v6.2d, v8.4s
  movi v7.16b, 0
  sadalp v7.2d, v8.4s

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40473	80110	101	80009	100	80013	0	300	0	320056	80113	200	0	80013	200	160026	1	160000	100
160204	40130	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320196	80148	200	0	80048	200	160024	1	160000	100
160204	40342	80110	101	80009	100	80013	0	300	0	320052	80112	200	0	80012	200	160024	1	160000	100
160204	40096	80110	101	80009	100	80013	0	300	0	320052	80112	200	0	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320200	80149	200	0	80049	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	160024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43887	80020	11	80009	10	80013	30	320052	80022	20	80012	20	160000	1	160000	10
160024	41272	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	41548	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160026	1	160000	10
160024	40499	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40388	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40392	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40413	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40400	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40388	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40417	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  sadalp v0.2d, v16.4s
  sadalp v1.2d, v16.4s
  sadalp v2.2d, v16.4s
  sadalp v3.2d, v16.4s
  sadalp v4.2d, v16.4s
  sadalp v5.2d, v16.4s
  sadalp v6.2d, v16.4s
  sadalp v7.2d, v16.4s
  sadalp v8.2d, v16.4s
  sadalp v9.2d, v16.4s
  sadalp v10.2d, v16.4s
  sadalp v11.2d, v16.4s
  sadalp v12.2d, v16.4s
  sadalp v13.2d, v16.4s
  sadalp v14.2d, v16.4s
  sadalp v15.2d, v16.4s

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80071	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320028	1	160000	100
160204	80035	160107	101	160006	0	100	160010	300	640208	160154	200	160061	200	320028	1	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640208	160154	200	160064	200	320024	1	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	80132	160017	11	160006	0	10	160010	0	30	0	640044	160020	20	0	160014	20	0	320000	1	0	160000	10
160024	80053	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160025	80071	160053	11	160042	0	10	160054	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	0	320000	1	0	160000	10

SADALP (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations