Icestorm: SADDLV (vector, 4H) measurements

Code:

  saddlv s0, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->2

Code:

  saddlv s0, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	769247	10131	200	10047	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10006	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 3: throughput

Count: 8

Code:

  saddlv s0, v8.4h
  saddlv s1, v8.4h
  saddlv s2, v8.4h
  saddlv s3, v8.4h
  saddlv s4, v8.4h
  saddlv s5, v8.4h
  saddlv s6, v8.4h
  saddlv s7, v8.4h

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	40079	80107	101	80006	0	100	80010	300	320036	80108	200	80012	200	0	160024	1	0	80000	100
80204	40045	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	160024	1	0	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320044	80110	200	80014	200	0	160028	1	0	80000	100
80204	40044	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	160024	1	0	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	160024	1	0	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	200	0	160024	1	0	80000	100
80204	40107	80157	101	80056	0	100	80060	300	320036	80108	200	80012	200	0	160024	1	0	80000	100
80204	40259	80256	101	80155	0	100	80159	300	320036	80108	200	80012	200	0	160024	1	0	80000	100
80204	40035	80105	101	80004	0	100	80008	300	320036	80108	200	80012	3027	2017	160132	1446	1029	80005	2012
80204	40035	80107	101	80006	0	100	80010	300	320036	80108	200	80012	200	0	160128	1	0	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40102	80027	21	80006	20	80010	0	70	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	160000	11	80000	10

SADDLV (vector, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations