Icestorm: SCVTF (scalar, fixed-point, D from W) measurements

Code:

  scvtf d0, w0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
2004	576	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	540	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Code:

  scvtf d0, w0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	100030	40101	10101	20000	10000	100	20000	10001	300	1546176	2578264	30101	200	10002	20004	200	10002	20004	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10020	20037	10002	10000	10000	10100
30204	100034	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10021	20039	10003	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10596	321	1576642	2629274	31699	206	10635	21246	215	10954	21872	10146	10000	10000	10100
30204	104241	40574	10245	20221	10108	117	21377	10768	330	1586350	2645348	32161	210	10827	21626	218	10933	21831	10144	10000	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30024	100069	40011	10011	20000	10000	10	20000	10000	30	1547712	2580760	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100033	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10017	30	1546384	2578617	30056	20	10021	20039	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010

Test 3: throughput

Count: 8

Code:

  scvtf d0, w8, #3
  scvtf d1, w8, #3
  scvtf d2, w8, #3
  scvtf d3, w8, #3
  scvtf d4, w8, #3
  scvtf d5, w8, #3
  scvtf d6, w8, #3
  scvtf d7, w8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	40160	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160205	40140	160175	101	80036	80038	100	80054	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	40540	160025	11	80006	80008	10	80012	80055	30	240273	640472	160120	20	80055	80055	20	80012	80012	1	80000	80000	10
160024	40068	160025	11	80006	80008	10	80012	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40044	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10

SCVTF (scalar, fixed-point, D from W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations