Icestorm: SCVTF (scalar, fixed-point, S from X) measurements

Code:

  scvtf s0, x0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
2004	591	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	653	2061	1	1030	1030	1042	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1042	3520	8680	2084	1042	1042	1000	1000	1	1000	1000
2004	602	2061	1	1030	1030	1042	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	540	2001	1	1000	1000	1000	1000	4114	9330	2000	1000	1000	1042	1042	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	4126	9342	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	608	2061	1	1030	1030	1042	1000	3000	8000	2000	1000	1000	1000	1000	1	1000	1000
2004	537	2001	1	1000	1000	1000	1042	4734	10118	2084	1042	1042	1000	1000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Code:

  scvtf s0, x0, #3
  fmov x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	100030	40101	10101	20000	10000	100	20000	10001	300	1546172	2578264	30101	200	10002	20004	200	10002	20004	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20004	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10021	20039	10002	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100041	40101	10101	20000	10000	100	20000	10000	300	1546190	2578290	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100
30204	100030	40101	10101	20000	10000	100	20000	10000	300	1546174	2578264	30100	200	10002	20002	200	10002	20002	10001	10000	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30024	100040	40011	10011	20000	10000	10	20000	10000	30	1546168	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100035	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10071	30	1549095	2583127	30198	20	10075	20145	20	10019	20037	10004	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010
30024	100030	40011	10011	20000	10000	10	20000	10000	30	1546174	2578264	30010	20	10000	20000	20	10000	20000	10001	10000	10000	10010

Test 3: throughput

Count: 8

Code:

  scvtf s0, x8, #3
  scvtf s1, x8, #3
  scvtf s2, x8, #3
  scvtf s3, x8, #3
  scvtf s4, x8, #3
  scvtf s5, x8, #3
  scvtf s6, x8, #3
  scvtf s7, x8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	40141	160115	101	80006	80008	100	80012	80054	300	240270	640464	160208	200	80054	80054	200	80012	80012	1	80000	80000	100
160204	40112	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80054	300	269734	674437	160208	200	80054	80054	200	80012	80012	1	80000	80000	100
160204	40111	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40096	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40101	160115	101	80006	80008	100	80012	80012	300	241086	641919	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40098	160115	101	80006	80008	100	80012	80012	300	241271	642113	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40090	160115	101	80006	80008	100	80012	80012	300	240036	640080	160124	200	80012	80012	200	80012	80012	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	40573	160027	11	80007	80009	10	80013	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40057	160011	11	80000	80000	10	80000	80000	30	276288	692287	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240992	640992	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40042	160011	11	80000	80000	10	80000	80000	30	240000	640000	160010	20	80000	80000	20	80054	80054	1	80000	80000	10

SCVTF (scalar, fixed-point, S from X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations