Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SHA1H

Test 1: uops

Code:

  sha1h s0, s0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	24769	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  sha1h s0, s0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10006	200	10006	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	10004	1	10000	100
10204	20081	10113	101	10012	100	10023	300	249769	10100	200	10004	200	10064	1	10000	100
10204	20081	10113	101	10012	100	10023	307	250237	10148	202	10064	200	10004	1	10000	100
10204	20082	10115	103	10012	102	10023	307	250003	10125	202	10036	200	10032	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	69	249907	10041	20	10035	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	10000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	10000	11	10000	10

Test 3: throughput

Count: 8

Code:

  sha1h s0, s8
  sha1h s1, s8
  sha1h s2, s8
  sha1h s3, s8
  sha1h s4, s8
  sha1h s5, s8
  sha1h s6, s8
  sha1h s7, s8

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	80048	80101	101	80000	0	100	80001	0	300	0	320005	80101	200	0	80008	200	0	80064	1	0	80000	100
80205	80068	80120	101	80019	0	100	80025	0	300	0	320005	80101	200	0	80008	200	0	80065	1	0	80000	100
80204	80034	80101	101	80000	0	100	80001	0	300	0	320005	80101	200	0	80008	200	0	80008	1	0	80000	100
80204	80034	80101	101	80000	0	100	80001	0	300	0	320005	80101	200	0	80008	200	0	80008	1	0	80000	100
80204	80083	80126	101	80025	0	100	80028	0	300	0	320212	80152	200	0	80064	200	0	80008	1	0	80000	100
80204	80034	80101	101	80000	0	100	80001	0	300	0	320005	80101	200	0	80008	200	0	80008	1	0	80000	100
80204	80034	80101	101	80000	0	100	80001	0	300	0	320092	80124	200	0	80036	200	0	80008	1	0	80000	100
80204	80034	80101	101	80000	0	100	80001	0	300	0	320005	80101	200	0	80008	200	0	80008	1	0	80000	100
80204	80034	80101	101	80000	0	100	80001	0	300	0	320005	80101	200	0	80008	200	0	80008	1	0	80000	100
80204	80082	80125	101	80024	0	100	80026	0	300	0	320005	80101	200	0	80008	200	0	80008	1	0	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	80034	80023	21	80002	20	80004	70	320000	80020	20	80000	20	80000	11	80000	10
80025	80068	80040	21	80019	20	80025	70	320010	80022	20	80008	20	80000	11	80000	10
80024	80034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10
80024	80034	80021	21	80000	20	80000	70	320000	80020	20	80000	20	80000	11	80000	10