Icestorm: SHA1M measurements

Code:

  sha1m q0, s1, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  sha1m q0, s1, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0034

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0034

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40034	10021	21	10000	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  sha1m q0, s0, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 5.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10006	200	30018	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10006	200	30099	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 5.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10025	50066	10025	21	10004	20	10016	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  sha1m q0, s1, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 5.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10006	200	30018	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10205	50066	10105	101	10004	100	10016	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 5.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	50033	10021	21	10000	20	10000	66	639686	10036	20	10032	20	30018	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10004	20	30012	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10004	20	30012	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10004	20	30012	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10004	20	30087	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10004	20	30012	11	10000	10
10024	50033	10021	21	10000	20	10000	68	639686	10036	20	10029	20	30012	11	10000	10
10025	50066	10025	21	10004	20	10016	70	639520	10020	20	10004	20	30012	11	10000	10
10025	50066	10025	21	10004	20	10016	69	639686	10036	20	10032	20	30012	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10004	20	30012	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha1m q0, s8, v9.4s
  movi v1.16b, 0
  sha1m q1, s8, v9.4s
  movi v2.16b, 0
  sha1m q2, s8, v9.4s
  movi v3.16b, 0
  sha1m q3, s8, v9.4s
  movi v4.16b, 0
  sha1m q4, s8, v9.4s
  movi v5.16b, 0
  sha1m q5, s8, v9.4s
  movi v6.16b, 0
  sha1m q6, s8, v9.4s
  movi v7.16b, 0
  sha1m q7, s8, v9.4s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	320034	80101	101	80000	100	80000	300	4079608	80100	200	80003	200	0	240084	1	0	160000	100
160205	320068	80106	101	80005	100	80017	300	4079608	80100	200	80002	200	0	240006	1	0	160000	100
160204	320034	80101	101	80000	100	80000	300	4079608	80100	200	80002	200	0	240006	1	0	160000	100
160204	320034	80101	101	80000	100	80000	300	4079783	80117	200	80028	200	0	240006	1	0	160000	100
160204	320034	80101	101	80000	100	80000	300	4079608	80100	200	80002	200	0	240006	1	0	160000	100
160205	320068	80106	101	80005	100	80017	300	4079608	80100	200	80002	200	0	240006	1	0	160000	100
160204	320034	80101	101	80000	100	80000	300	4079608	80100	200	80002	200	0	240006	1	0	160000	100
160204	320034	80101	101	80000	100	80000	300	4079608	80100	200	80002	200	0	240006	1	0	160000	100
160204	320034	80101	101	80000	100	80000	300	4079608	80100	200	80002	200	0	240006	1	0	160000	100
160205	320068	80106	101	80005	100	80017	300	4079608	80100	200	80003	200	0	240006	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	320034	80011	11	80000	10	80000	30	4079608	80010	20	80002	20	0	240000	1	0	160000	10
160025	320068	80016	11	80005	10	80017	30	4080331	80063	20	80077	20	0	240000	1	0	160000	10
160024	320034	80011	11	80000	10	80000	30	4079783	80027	20	80026	20	0	240000	1	0	160000	10
160025	320068	80016	11	80005	10	80017	30	4079608	80010	20	80000	20	0	240000	1	0	160000	10
160024	320034	80011	11	80000	10	80000	30	4079608	80010	20	80000	20	0	240078	1	0	160000	10
160024	320034	80011	11	80000	10	80000	30	4079608	80010	20	80000	20	0	240000	1	0	160000	10
160024	320034	80011	11	80000	10	80000	30	4079608	80010	20	80000	20	0	240084	1	0	160000	10
160024	320034	80011	11	80000	10	80000	30	4079608	80010	20	80000	20	0	240000	1	0	160000	10
160024	320034	80011	11	80000	10	80000	30	4079783	80027	20	80026	20	0	240000	1	0	160000	10
160024	320034	80011	11	80000	10	80000	30	4079608	80010	20	80000	20	0	240078	1	0	160000	10

Test 6: throughput

Count: 4

Code:

  sha1m q0, s4, v5.4s
  sha1m q1, s4, v5.4s
  sha1m q2, s4, v5.4s
  sha1m q3, s4, v5.4s

Initialization

  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 4.0008

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
40204	160034	40101	101	40000	100	40000	300	2039608	40100	200	40006	200	0	120018	1	0	40000	100
40204	160034	40101	101	40000	100	40000	300	2039608	40100	200	40004	200	0	120012	1	0	40000	100
40204	160034	40101	101	40000	100	40000	300	2039608	40100	200	40004	200	0	120012	1	0	40000	100
40205	160068	40106	101	40005	100	40017	300	2039608	40100	200	40004	200	0	120012	1	0	40000	100
40204	160034	40101	101	40000	100	40000	300	2039608	40100	200	40004	200	0	120012	1	0	40000	100
40204	160034	40101	101	40000	100	40000	300	2039608	40100	200	40004	200	0	120096	1	0	40000	100
40204	160034	40101	101	40000	100	40000	300	2039608	40100	200	40004	200	0	120096	1	0	40000	100
40205	160068	40106	101	40005	100	40017	300	2039608	40100	200	40006	200	0	120012	1	0	40000	100
40204	160034	40101	101	40000	100	40000	300	2039608	40100	200	40006	200	0	120012	1	0	40000	100
40204	160034	40101	101	40000	100	40000	300	2039608	40100	200	40004	200	0	120012	1	0	40000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 4.0008

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
40024	160034	40011	11	40000	0	10	40000	30	2039608	40010	20	40006	20	0	120000	1	0	40000	10
44684	177291	44272	2598	40049	1625	2493	40050	30	2039608	40010	20	40000	20	0	120000	1	0	40000	10
40024	160034	40011	11	40000	0	10	40000	30	2039608	40010	20	40000	20	0	120000	1	0	40000	10
40024	160034	40011	11	40000	0	10	40000	30	2039608	40010	20	40000	20	0	120000	1	0	40000	10
40024	160034	40011	11	40000	0	10	40000	30	2039608	40010	20	40000	20	0	120000	1	0	40000	10
40025	160068	40016	11	40005	0	10	40017	30	2039608	40010	20	40000	20	0	120000	1	0	40000	10
40024	160034	40011	11	40000	0	10	40000	30	2039608	40010	20	40000	20	0	120000	1	0	40000	10
40024	160034	40011	11	40000	0	10	40000	30	2039608	40010	20	40000	20	0	120000	1	0	40000	10
40024	160034	40011	11	40000	0	10	40000	30	2039608	40010	20	40000	20	0	120084	1	0	40000	10
40024	160034	40011	11	40000	0	10	40000	30	2039608	40010	20	40000	20	0	120000	1	0	40000	10

SHA1M

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations