Icestorm: SHA1SU0 measurements

Code:

  sha1su0 v0.4s, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  sha1su0 v0.4s, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249767	10020	20	10004	20	30012	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  sha1su0 v0.4s, v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10006	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10006	200	30018	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	249768	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  sha1su0 v0.4s, v1.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30018	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	249768	10020	20	10006	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha1su0 v0.4s, v8.4s, v9.4s
  movi v1.16b, 0
  sha1su0 v1.4s, v8.4s, v9.4s
  movi v2.16b, 0
  sha1su0 v2.4s, v8.4s, v9.4s
  movi v3.16b, 0
  sha1su0 v3.4s, v8.4s, v9.4s
  movi v4.16b, 0
  sha1su0 v4.4s, v8.4s, v9.4s
  movi v5.16b, 0
  sha1su0 v5.4s, v8.4s, v9.4s
  movi v6.16b, 0
  sha1su0 v6.4s, v8.4s, v9.4s
  movi v7.16b, 0
  sha1su0 v7.4s, v8.4s, v9.4s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80077	80101	101	80000	100	80001	300	320088	80123	200	80034	200	240021	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320010	80102	200	80007	200	240018	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80125	80011	11	80000	10	80001	30	320010	80012	20	80007	20	240000	1	160000	10
160024	80038	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240096	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 4

Code:

  sha1su0 v0.4s, v4.4s, v5.4s
  sha1su0 v1.4s, v4.4s, v5.4s
  sha1su0 v2.4s, v4.4s, v5.4s
  sha1su0 v3.4s, v4.4s, v5.4s

Initialization

  movi v4.16b, 5
  movi v5.16b, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0009

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40204	40034	40101	101	40000	0	100	40001	300	160014	40103	200	40010	200	120024	1	40000	100
40204	40034	40101	101	40000	0	100	40001	300	160005	40101	200	40008	200	120024	1	40000	100
40204	40034	40101	101	40000	0	100	40001	300	160005	40101	200	40008	200	120024	1	40000	100
40204	40034	40101	101	40000	0	100	40001	300	160005	40101	200	40008	200	120024	1	40000	100
40204	40034	40101	101	40000	0	100	40001	300	160005	40101	200	40008	200	120024	1	40000	100
40204	40034	40101	101	40000	0	100	40001	300	160005	40101	200	40008	200	120024	1	40000	100
40204	40034	40101	101	40000	0	100	40001	300	160005	40101	200	40008	200	120024	1	40000	100
40204	40034	40101	101	40000	0	100	40001	300	160005	40101	200	40008	200	120024	1	40000	100
40204	40034	40101	101	40000	0	100	40001	300	160005	40101	200	40008	200	120024	1	40000	100
40204	40034	40101	101	40000	0	100	40001	300	160005	40101	200	40008	200	120120	1	40000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0009

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
40024	40048	40011	11	40000	10	40001	30	160000	40010	20	40000	20	120000	1	40000	10
40025	40068	40029	11	40018	10	40024	30	160000	40010	20	40000	20	120000	1	40000	10
40024	40034	40011	11	40000	10	40000	30	160000	40010	20	40000	20	120000	1	40000	10
40024	40034	40011	11	40000	10	40000	30	160000	40010	20	40000	20	120000	1	40000	10
40024	40034	40011	11	40000	10	40000	30	160000	40010	20	40000	20	120000	1	40000	10
40024	40034	40011	11	40000	10	40000	30	160000	40010	20	40000	20	120000	1	40000	10
40024	40034	40011	11	40000	10	40000	30	160000	40010	20	40000	20	120000	1	40000	10
40024	40034	40011	11	40000	10	40000	30	160000	40010	20	40000	20	120000	1	40000	10
40024	40034	40011	11	40000	10	40000	30	160000	40010	20	40000	20	120000	1	40000	10
40024	40034	40011	11	40000	10	40000	30	160000	40010	20	40000	20	120000	1	40000	10

SHA1SU0

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations