Icestorm: SHA1SU1 measurements

Code:

  sha1su1 v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  sha1su1 v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10006	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249907	10121	200	10036	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  sha1su1 v0.4s, v0.4s

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10205	20066	10109	101	10008	0	100	10021	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10004	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	68	249907	10041	20	10032	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha1su1 v0.4s, v8.4s
  movi v1.16b, 0
  sha1su1 v1.4s, v8.4s
  movi v2.16b, 0
  sha1su1 v2.4s, v8.4s
  movi v3.16b, 0
  sha1su1 v3.4s, v8.4s
  movi v4.16b, 0
  sha1su1 v4.4s, v8.4s
  movi v5.16b, 0
  sha1su1 v5.4s, v8.4s
  movi v6.16b, 0
  sha1su1 v6.4s, v8.4s
  movi v7.16b, 0
  sha1su1 v7.4s, v8.4s

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80066	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80006	200	160012	1	160000	100
160204	80034	80101	101	80000	100	80002	0	300	0	320005	80101	200	0	80006	200	160012	1	160000	100
160204	80034	80101	101	80000	100	80002	0	300	0	320409	80201	200	0	80111	200	160012	1	160000	100
160204	80034	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80006	200	160012	1	160000	100
160204	80034	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80006	200	160012	1	160000	100
160204	80034	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80006	200	160012	1	160000	100
160204	80034	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80006	200	160012	1	160000	100
160204	80034	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80006	200	160012	1	160000	100
160204	80318	80197	101	80096	100	80102	0	300	0	320088	80123	200	0	80033	200	160012	1	160000	100
160204	80034	80101	101	80000	100	80002	0	300	0	320005	80101	200	0	80006	200	160012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80142	80011	11	80000	10	80002	30	320000	80010	20	80000	20	160000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160025	80068	80028	11	80017	10	80023	30	320000	80010	20	80000	20	160000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  sha1su1 v0.4s, v16.4s
  sha1su1 v1.4s, v16.4s
  sha1su1 v2.4s, v16.4s
  sha1su1 v3.4s, v16.4s
  sha1su1 v4.4s, v16.4s
  sha1su1 v5.4s, v16.4s
  sha1su1 v6.4s, v16.4s
  sha1su1 v7.4s, v16.4s
  sha1su1 v8.4s, v16.4s
  sha1su1 v9.4s, v16.4s
  sha1su1 v10.4s, v16.4s
  sha1su1 v11.4s, v16.4s
  sha1su1 v12.4s, v16.4s
  sha1su1 v13.4s, v16.4s
  sha1su1 v14.4s, v16.4s
  sha1su1 v15.4s, v16.4s

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	160082	160118	101	160017	100	160022	300	640005	160101	200	160008	200	0	320016	1	0	160000	100
160204	160034	160101	101	160000	100	160001	300	640005	160101	200	160008	200	0	320016	1	0	160000	100
160204	160034	160101	101	160000	100	160001	300	640005	160101	200	160008	200	0	320016	1	0	160000	100
160204	160034	160101	101	160000	100	160001	300	640005	160101	200	160008	200	0	320016	1	0	160000	100
160204	160034	160101	101	160000	100	160001	300	640005	160101	200	160008	200	0	320016	1	0	160000	100
160205	160068	160118	101	160017	100	160022	300	640005	160101	200	160008	200	0	320016	1	0	160000	100
160204	160034	160101	101	160000	100	160001	300	640005	160101	200	160008	200	0	320016	1	0	160000	100
160204	160034	160101	101	160000	100	160001	300	640005	160101	200	160008	200	0	320016	1	0	160000	100
160204	160034	160101	101	160000	100	160001	300	640005	160101	200	160008	200	0	320072	1	0	160000	100
160204	160034	160101	101	160000	100	160001	300	640005	160101	200	160008	200	0	320016	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	160040	160012	11	160001	10	160003	30	640000	160010	20	160000	20	320000	1	160000	10
160024	160034	160011	11	160000	10	160000	30	640092	160034	20	160037	20	320000	1	160000	10
160024	160034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	160034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	160034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	160034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	160034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	160034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	160034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	160034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10

SHA1SU1

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations