Icestorm: SHA256H measurements

Code:

  sha256h q0, q1, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3072	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  sha256h q0, q1, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0034

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0034

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40034	10021	21	10000	20	10000	70	509608	10020	20	10004	20	30012	11	10000	10
10024	40034	10021	21	10000	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	20	10000	70	509882	10038	20	10024	20	31065	11	10000	10
10024	41005	10161	21	10140	20	10360	69	514266	10326	20	10430	20	30687	11	10000	10
10024	41102	10179	25	10154	24	10396	70	515811	10433	20	10587	24	31674	13	10000	10
10024	41154	10182	21	10161	20	10414	76	515651	10419	22	10560	20	31524	11	10000	10
10024	40799	10126	21	10105	20	10270	67	514266	10326	20	10431	22	31359	12	10000	10
10024	40907	10147	21	10126	20	10324	67	514540	10344	20	10460	22	31602	12	10000	10

Test 3: Latency 1->2

Code:

  sha256h q0, q0, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 5.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10006	200	30018	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10006	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30084	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 5.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10006	20	30018	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  sha256h q0, q1, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 5.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	50128	10111	101	10010	100	10034	300	639520	10100	200	10006	200	30012	1	10000	100
10204	50365	10138	103	10035	102	10119	316	641088	10207	206	10152	200	30168	1	10000	100
10204	50177	10120	105	10015	104	10051	300	639686	10116	200	10032	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 5.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10006	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10004	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha256h q0, q8, v9.4s
  movi v1.16b, 0
  sha256h q1, q8, v9.4s
  movi v2.16b, 0
  sha256h q2, q8, v9.4s
  movi v3.16b, 0
  sha256h q3, q8, v9.4s
  movi v4.16b, 0
  sha256h q4, q8, v9.4s
  movi v5.16b, 0
  sha256h q5, q8, v9.4s
  movi v6.16b, 0
  sha256h q6, q8, v9.4s
  movi v7.16b, 0
  sha256h q7, q8, v9.4s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	160035	80101	101	80000	0	100	80000	300	1999757	80100	200	80005	200	240012	1	160000	100
160204	160035	80101	101	80000	0	100	80000	300	1999758	80100	200	80004	200	240015	1	160000	100
160204	160035	80101	101	80000	0	100	80000	300	1999758	80100	200	80004	200	240102	1	160000	100
160204	160035	80101	101	80000	0	100	80000	300	2001002	80266	200	80208	202	240366	2	160000	100
160204	160035	80101	101	80000	0	100	80000	300	1999758	80100	200	80004	200	240102	1	160000	100
160204	160035	80101	101	80000	0	100	80000	300	1999758	80100	200	80004	200	240012	1	160000	100
160204	160035	80101	101	80000	0	100	80000	300	1999758	80100	200	80004	200	240012	1	160000	100
160204	160035	80101	101	80000	0	100	80000	300	1999758	80100	200	80004	200	240012	1	160000	100
160204	160035	80101	101	80000	0	100	80000	300	1999758	80100	200	80004	200	240012	1	160000	100
160204	160035	80101	101	80000	0	100	80000	300	1999758	80100	200	80004	200	240102	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	160035	80011	11	80000	0	10	80000	0	30	0	1999915	80032	20	0	80033	20	240015	1	160000	10
160024	160035	80011	11	80000	0	10	80000	0	30	0	1999758	80010	20	0	80000	20	240000	1	160000	10
160024	160035	80011	11	80000	0	10	80000	0	30	0	1999916	80032	20	0	80034	20	240000	1	160000	10
160024	160192	80011	11	80000	0	10	80000	12536	453444	264821	1381143	84696	22853	14151	55429	20	240015	1	160000	10
160024	160035	80011	11	80000	0	10	80000	0	30	0	1999758	80010	20	0	80000	20	240102	1	160000	10
152563	149522	82703	8484	68977	5242	8018	68637	0	30	0	1999769	80034	20	0	80028	20	240000	1	160000	10
160024	160035	80011	11	80000	0	10	80000	0	30	0	1999758	80010	20	0	80000	20	240000	1	160000	10
160024	160035	80011	11	80000	0	10	80000	0	30	0	1999758	80010	20	0	80000	20	240000	1	160000	10
160024	160035	80011	11	80000	0	10	80000	0	30	0	1999915	80032	20	0	80033	20	240096	1	160000	10
160024	160035	80011	11	80000	0	10	80000	0	30	0	1999758	80010	20	0	80000	20	240000	1	160000	10

Test 6: throughput

Count: 16

Code:

  sha256h q0, q16, v17.4s
  sha256h q1, q16, v17.4s
  sha256h q2, q16, v17.4s
  sha256h q3, q16, v17.4s
  sha256h q4, q16, v17.4s
  sha256h q5, q16, v17.4s
  sha256h q6, q16, v17.4s
  sha256h q7, q16, v17.4s
  sha256h q8, q16, v17.4s
  sha256h q9, q16, v17.4s
  sha256h q10, q16, v17.4s
  sha256h q11, q16, v17.4s
  sha256h q12, q16, v17.4s
  sha256h q13, q16, v17.4s
  sha256h q14, q16, v17.4s
  sha256h q15, q16, v17.4s

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	320035	160101	101	160000	100	160000	0	300	0	3999757	160100	200	0	160006	200	480012	1	160000	100
160204	320035	160101	101	160000	100	160000	0	300	0	3999916	160122	200	0	160036	200	480012	1	160000	100
160204	320035	160101	101	160000	100	160000	0	300	0	3999758	160100	200	0	160004	200	480012	1	160000	100
160204	320035	160101	101	160000	100	160000	0	300	0	3999915	160122	200	0	160034	200	480012	1	160000	100
160204	320035	160101	101	160000	100	160000	0	300	0	3999758	160100	200	0	160004	200	480108	1	160000	100
160204	320035	160101	101	160000	100	160000	0	300	0	3999916	160122	200	0	160032	200	480012	1	160000	100
160204	320035	160101	101	160000	100	160000	0	300	0	3999758	160100	200	0	160004	200	480012	1	160000	100
160204	320035	160101	101	160000	100	160000	0	300	0	3999758	160100	200	0	160004	200	480012	1	160000	100
160204	320035	160101	101	160000	100	160000	0	300	0	3999758	160100	200	0	160004	200	480012	1	160000	100
160204	320035	160101	101	160000	100	160000	0	300	0	3999758	160100	200	0	160004	200	480012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	320035	160011	11	160000	0	10	160000	30	3999757	160010	20	160006	20	0	480000	1	0	160000	10
160024	320035	160011	11	160000	0	10	160000	30	3999930	160032	20	160036	20	0	480000	1	0	160000	10
160024	320035	160011	11	160000	0	10	160000	30	3999930	160032	20	160036	20	0	480000	1	0	160000	10
160025	320072	160021	11	160010	0	10	160022	30	3999758	160010	20	160004	20	0	480000	1	0	160000	10
160024	320035	160011	11	160000	0	10	160000	30	3999758	160010	20	160000	20	0	480105	1	0	160000	10
160024	320035	160011	11	160000	0	10	160000	30	3999758	160010	20	160000	20	0	480000	1	0	160000	10
160024	320035	160011	11	160000	0	10	160000	30	3999758	160010	20	160000	20	0	480108	1	0	160000	10
160024	320035	160011	11	160000	0	10	160000	30	3999916	160032	20	160036	20	0	480000	1	0	160000	10
160024	320035	160011	11	160000	0	10	160000	30	3999758	160010	20	160000	20	0	480000	1	0	160000	10
160024	320035	160011	11	160000	0	10	160000	30	3999916	160032	20	160036	20	0	480000	1	0	160000	10

SHA256H

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations