Icestorm: SHA256H2 measurements

Code:

  sha256h2 q0, q1, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000
1004	4034	1001	1	1000	1000	50608	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  sha256h2 q0, q1, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 4.0034

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100
10204	40034	10101	101	10000	100	10000	300	509608	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 4.0034

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	40034	10021	21	10000	0	20	10000	70	509608	10020	20	10004	20	30000	11	10000	10
10024	40034	10021	21	10000	0	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	0	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	0	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	0	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	0	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	0	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	0	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10024	40034	10021	21	10000	0	20	10000	70	509608	10020	20	10000	20	30000	11	10000	10
10025	40068	10026	21	10005	0	20	10017	70	509608	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  sha256h2 q0, q0, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 5.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10006	200	0	30018	1	0	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	0	30012	1	0	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	0	30012	1	0	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	0	30012	1	0	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	0	30012	1	0	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	0	30012	1	0	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	0	30012	1	0	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	0	30012	1	0	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	0	30012	1	0	10000	100
10204	50033	10101	101	10000	100	10000	300	639686	10116	200	10028	200	0	30012	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 5.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10

Test 4: Latency 1->3

Code:

  sha256h2 q0, q1, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 5.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10006	200	30018	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10205	50066	10105	101	10004	100	10016	300	639520	10100	200	10004	200	30018	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100
10204	50033	10101	101	10000	100	10000	300	639520	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 5.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10006	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639686	10036	20	10032	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10
10024	50033	10021	21	10000	20	10000	70	639520	10020	20	10000	20	0	30000	11	0	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha256h2 q0, q8, v9.4s
  movi v1.16b, 0
  sha256h2 q1, q8, v9.4s
  movi v2.16b, 0
  sha256h2 q2, q8, v9.4s
  movi v3.16b, 0
  sha256h2 q3, q8, v9.4s
  movi v4.16b, 0
  sha256h2 q4, q8, v9.4s
  movi v5.16b, 0
  sha256h2 q5, q8, v9.4s
  movi v6.16b, 0
  sha256h2 q6, q8, v9.4s
  movi v7.16b, 0
  sha256h2 q7, q8, v9.4s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	160035	80101	101	80000	0	100	80000	0	300	0	1999757	80100	200	0	80005	200	240012	1	160000	100
160204	160035	80101	101	80000	0	100	80000	0	300	0	1999758	80100	200	0	80004	200	240012	1	160000	100
160204	160035	80101	101	80000	0	100	80000	0	300	0	1999930	80122	200	0	80034	200	240015	1	160000	100
160204	160035	80101	101	80000	0	100	80000	0	300	0	1999758	80100	200	0	80004	200	240012	1	160000	100
160204	160035	80101	101	80000	0	100	80000	0	300	0	1999758	80100	200	0	80004	200	240012	1	160000	100
160204	160035	80101	101	80000	0	100	80000	0	300	0	1999758	80100	200	0	80004	200	240012	1	160000	100
160204	160035	80101	101	80000	0	100	80000	0	300	0	1999758	80100	200	0	80004	202	240099	2	160000	100
160205	160070	80111	101	80010	0	100	80022	0	300	0	1999758	80100	200	0	80004	200	240012	1	160000	100
160204	160035	80101	101	80000	0	100	80000	0	300	0	1999758	80100	200	0	80004	200	240096	1	160000	100
169642	197455	88471	5521	79962	2988	5145	79978	0	300	0	1999757	80100	200	0	80005	200	240012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	160035	80011	11	80000	10	80000	0	30	0	1999757	80010	20	0	80005	20	0	240000	1	0	160000	10
160024	160035	80011	11	80000	10	80000	0	30	0	1999758	80010	20	0	80000	20	0	240000	1	0	160000	10
160024	160035	80011	11	80000	10	80000	0	30	0	1999758	80010	20	0	80000	20	0	240000	1	0	160000	10
160024	160035	80011	11	80000	10	80000	0	30	0	1999758	80010	20	0	80000	20	0	240000	1	0	160000	10
160024	160035	80011	11	80000	10	80000	0	30	0	1999758	80010	20	0	80000	20	0	240000	1	0	160000	10
160024	160035	80011	11	80000	10	80000	0	30	0	1999758	80010	20	0	80000	20	0	240000	1	0	160000	10
160024	160035	80011	11	80000	10	80000	0	30	0	1999758	80010	20	0	80000	20	0	240000	1	0	160000	10
160025	160072	80021	11	80010	10	80022	0	30	0	1999758	80010	20	0	80000	3121	5631	240290	1282	2663	160039	1898
160024	160035	80011	11	80000	10	80000	0	30	0	1999758	80010	20	0	80000	20	0	240000	1	0	160000	10
160024	160035	80011	11	80000	10	80000	0	30	0	1999758	80010	20	0	80000	20	0	240000	1	0	160000	10

Test 6: throughput

Count: 16

Code:

  sha256h2 q0, q16, v17.4s
  sha256h2 q1, q16, v17.4s
  sha256h2 q2, q16, v17.4s
  sha256h2 q3, q16, v17.4s
  sha256h2 q4, q16, v17.4s
  sha256h2 q5, q16, v17.4s
  sha256h2 q6, q16, v17.4s
  sha256h2 q7, q16, v17.4s
  sha256h2 q8, q16, v17.4s
  sha256h2 q9, q16, v17.4s
  sha256h2 q10, q16, v17.4s
  sha256h2 q11, q16, v17.4s
  sha256h2 q12, q16, v17.4s
  sha256h2 q13, q16, v17.4s
  sha256h2 q14, q16, v17.4s
  sha256h2 q15, q16, v17.4s

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	320035	160101	101	160000	100	160000	300	3999757	160100	200	160006	200	480018	1	160000	100
160205	320072	160111	101	160010	100	160022	300	3999930	160122	200	160033	200	480012	1	160000	100
160205	320072	160111	101	160010	100	160022	300	3999758	160100	200	160004	200	480012	1	160000	100
160204	320035	160101	101	160000	100	160000	300	3999758	160100	200	160004	200	480096	1	160000	100
160204	320035	160101	101	160000	100	160000	300	3999758	160100	200	160004	200	480012	1	160000	100
160204	320035	160101	101	160000	100	160000	300	3999758	160100	200	160004	200	480012	1	160000	100
160204	320035	160101	101	160000	100	160000	300	3999916	160122	200	160035	200	480012	1	160000	100
160204	320035	160101	101	160000	100	160000	300	3999758	160100	200	160004	200	480012	1	160000	100
160204	320035	160101	101	160000	100	160000	300	3999758	160100	200	160004	200	480012	1	160000	100
160205	320072	160111	101	160010	100	160022	300	3999758	160100	200	160004	200	480012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	320035	160011	11	160000	0	10	160000	30	3999757	160010	20	160000	20	480000	1	160000	10
160024	320035	160011	11	160000	0	10	160000	30	3999916	160032	20	160036	20	480000	1	160000	10
160024	320035	160011	11	160000	0	10	160000	30	3999758	160010	20	160000	20	480000	1	160000	10
160024	320035	160011	11	160000	0	10	160000	30	4000088	160054	20	160063	20	480000	1	160000	10
160024	320035	160011	11	160000	0	10	160000	30	3999758	160010	20	160000	20	480000	1	160000	10
160024	320035	160011	11	160000	0	10	160000	30	3999916	160032	20	160037	20	480000	1	160000	10
160024	320035	160011	11	160000	0	10	160000	30	3999758	160010	20	160000	20	480000	1	160000	10
160025	320070	160021	11	160010	0	10	160022	30	3999758	160010	20	160000	20	480000	1	160000	10
160025	320070	160021	11	160010	0	10	160022	30	3999758	160010	20	160000	20	480000	1	160000	10
160024	320035	160011	11	160000	0	10	160000	30	3999757	160010	20	160000	20	480000	1	160000	10

SHA256H2

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations