Icestorm: SHA256SU1 measurements

Code:

  sha256su1 v0.4s, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	37694	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	37694	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  sha256su1 v0.4s, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	67	379850	10038	20	10032	20	30012	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30096	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  sha256su1 v0.4s, v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10006	200	30018	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10205	30066	10109	103	10006	102	10018	300	379694	10100	200	10006	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  sha256su1 v0.4s, v1.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10006	200	30018	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30129	10119	103	10016	102	10040	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	379694	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	69	379850	10038	20	10032	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10025	30066	10027	21	10006	20	10018	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	379694	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha256su1 v0.4s, v8.4s, v9.4s
  movi v1.16b, 0
  sha256su1 v1.4s, v8.4s, v9.4s
  movi v2.16b, 0
  sha256su1 v2.4s, v8.4s, v9.4s
  movi v3.16b, 0
  sha256su1 v3.4s, v8.4s, v9.4s
  movi v4.16b, 0
  sha256su1 v4.4s, v8.4s, v9.4s
  movi v5.16b, 0
  sha256su1 v5.4s, v8.4s, v9.4s
  movi v6.16b, 0
  sha256su1 v6.4s, v8.4s, v9.4s
  movi v7.16b, 0
  sha256su1 v7.4s, v8.4s, v9.4s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80096	80101	101	80000	0	100	80001	300	320010	80102	200	80007	200	240021	1	160000	100
160204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80035	80101	101	80000	0	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80189	80011	11	80000	10	80002	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80054	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80035	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80035	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80035	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80035	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80035	80011	11	80000	10	80000	30	320087	80033	20	80033	20	240000	1	160000	10
160024	80035	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80035	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80035	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 16

Code:

  sha256su1 v0.4s, v16.4s, v17.4s
  sha256su1 v1.4s, v16.4s, v17.4s
  sha256su1 v2.4s, v16.4s, v17.4s
  sha256su1 v3.4s, v16.4s, v17.4s
  sha256su1 v4.4s, v16.4s, v17.4s
  sha256su1 v5.4s, v16.4s, v17.4s
  sha256su1 v6.4s, v16.4s, v17.4s
  sha256su1 v7.4s, v16.4s, v17.4s
  sha256su1 v8.4s, v16.4s, v17.4s
  sha256su1 v9.4s, v16.4s, v17.4s
  sha256su1 v10.4s, v16.4s, v17.4s
  sha256su1 v11.4s, v16.4s, v17.4s
  sha256su1 v12.4s, v16.4s, v17.4s
  sha256su1 v13.4s, v16.4s, v17.4s
  sha256su1 v14.4s, v16.4s, v17.4s
  sha256su1 v15.4s, v16.4s, v17.4s

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	160091	160120	101	160019	100	160025	300	640087	160123	200	160038	200	0	480117	1	0	160000	100
160204	160035	160101	101	160000	100	160001	300	640005	160101	200	160008	200	0	480024	1	0	160000	100
160204	160035	160101	101	160000	100	160001	300	640005	160101	200	160008	200	0	480024	1	0	160000	100
160204	160035	160101	101	160000	100	160001	300	640005	160101	200	160008	200	0	480123	1	0	160000	100
160204	160035	160101	101	160000	100	160001	300	640005	160101	200	160008	200	0	480024	1	0	160000	100
160205	160081	160119	101	160018	100	160024	300	640014	160103	200	160010	200	0	480024	1	0	160000	100
160205	160070	160119	101	160018	100	160024	300	640005	160101	200	160008	200	0	480108	1	0	160000	100
160204	160035	160101	101	160000	100	160001	300	640100	160126	200	160040	200	0	480024	1	0	160000	100
160206	160112	160137	101	160036	100	160046	300	640005	160101	200	160008	200	0	480024	1	0	160000	100
160204	160035	160101	101	160000	100	160001	307	640096	160127	202	160038	200	0	480114	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	160035	160011	11	160000	0	10	160001	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	160035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	160035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	160035	160011	11	160000	0	10	160000	0	30	0	640100	160036	20	0	160040	20	480000	1	160000	10
160024	160035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	160035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	160035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	160035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	160035	160011	11	160000	0	10	160000	0	30	0	640087	160033	20	0	160036	20	480000	1	160000	10
160024	160035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10

SHA256SU1

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations