Icestorm: SHA512SU0 measurements

Code:

  sha512su0 v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  sha512su0 v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10006	200	20012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249907	10121	200	10032	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	249768	10020	20	10006	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	66	249907	10041	20	10035	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  sha512su0 v0.2d, v0.2d

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10004	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha512su0 v0.2d, v8.2d
  movi v1.16b, 0
  sha512su0 v1.2d, v8.2d
  movi v2.16b, 0
  sha512su0 v2.2d, v8.2d
  movi v3.16b, 0
  sha512su0 v3.2d, v8.2d
  movi v4.16b, 0
  sha512su0 v4.2d, v8.2d
  movi v5.16b, 0
  sha512su0 v5.2d, v8.2d
  movi v6.16b, 0
  sha512su0 v6.2d, v8.2d
  movi v7.16b, 0
  sha512su0 v7.2d, v8.2d

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	80091	80101	101	80000	100	80002	0	300	0	320005	80101	200	0	80006	200	0	160014	1	0	160000	100
160204	80034	80101	101	80000	100	80002	0	300	0	320005	80101	200	0	80006	200	0	160014	1	0	160000	100
160204	80034	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80006	200	0	160012	1	0	160000	100
160204	80034	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80006	200	0	160012	1	0	160000	100
160204	80034	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80006	200	0	160012	1	0	160000	100
160204	80034	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80006	200	0	160012	1	0	160000	100
160204	80034	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80006	200	0	160012	1	0	160000	100
160205	80074	80118	101	80017	100	80022	0	300	0	320005	80101	200	0	80006	200	0	160012	1	0	160000	100
160204	80034	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80006	200	0	160012	1	0	160000	100
160204	80034	80101	101	80000	100	80001	0	300	0	320005	80101	200	0	80006	200	0	160012	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80225	80011	11	80000	10	80002	30	320005	80011	20	80006	20	160012	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160025	80068	80028	11	80017	10	80023	30	320005	80011	20	80006	20	160000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320101	80035	20	80027	20	160000	1	160000	10
160024	80175	80059	11	80048	10	80050	30	320000	80010	20	80000	20	160052	1	160000	10
160024	80034	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	80104	80035	11	80024	10	80025	30	320101	80035	20	80026	20	160158	1	160000	10

Test 5: throughput

Count: 16

Code:

  sha512su0 v0.2d, v16.2d
  sha512su0 v1.2d, v16.2d
  sha512su0 v2.2d, v16.2d
  sha512su0 v3.2d, v16.2d
  sha512su0 v4.2d, v16.2d
  sha512su0 v5.2d, v16.2d
  sha512su0 v6.2d, v16.2d
  sha512su0 v7.2d, v16.2d
  sha512su0 v8.2d, v16.2d
  sha512su0 v9.2d, v16.2d
  sha512su0 v10.2d, v16.2d
  sha512su0 v11.2d, v16.2d
  sha512su0 v12.2d, v16.2d
  sha512su0 v13.2d, v16.2d
  sha512su0 v14.2d, v16.2d
  sha512su0 v15.2d, v16.2d

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	160048	160101	101	160000	0	100	160001	0	300	0	640005	160101	200	0	160008	200	320016	1	160000	100
160204	160034	160101	101	160000	0	100	160001	0	300	0	640005	160101	200	0	160008	200	320130	1	160000	100
160204	160231	160199	101	160098	0	100	160104	0	300	0	640464	160218	200	0	160145	200	320072	1	160000	100
160204	160083	160127	101	160026	0	100	160029	0	300	0	640321	160179	200	0	160095	200	320072	1	160000	100
160204	160034	160101	101	160000	0	100	160001	0	300	0	640005	160101	200	0	160008	200	320128	1	160000	100
90592	97437	90177	3873	84090	2214	3926	84100	0	300	0	640005	160101	200	0	160008	200	320016	1	160000	100
160204	160034	160101	101	160000	0	100	160001	0	300	0	640005	160101	200	0	160008	200	320016	1	160000	100
160204	160034	160101	101	160000	0	100	160001	0	300	0	640005	160101	200	0	160008	200	320016	1	160000	100
160204	160034	160101	101	160000	0	100	160001	0	300	0	640092	160124	200	0	160036	200	320016	1	160000	100
160205	160068	160118	101	160017	0	100	160022	0	300	0	640005	160101	200	0	160008	200	320016	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	160040	160012	11	160001	10	160003	30	640005	160011	20	160008	20	320000	1	160000	10
160024	160034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	160034	160012	11	160001	10	160003	30	640000	160010	20	160000	20	320000	1	160000	10
160024	160034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	160034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320074	1	160000	10
160025	160075	160028	11	160017	10	160022	30	640000	160010	20	160000	20	320000	1	160000	10
160024	160034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	160034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	160034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320076	1	160000	10
160024	160060	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10

SHA512SU0

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations