Icestorm: SHA512SU1 measurements

Code:

  sha512su1 v0.2d, v1.2d, v2.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000
1004	2033	1001	1	1000	1000	24769	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  sha512su1 v0.2d, v1.2d, v2.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	249768	10020	20	10006	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249907	10041	20	10035	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30012	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10025	20066	10029	21	10008	20	10021	70	249769	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  sha512su1 v0.2d, v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10006	200	30012	1	10000	100
10205	20066	10109	101	10008	0	100	10021	300	249769	10100	200	10004	200	30012	1	10000	100
10205	20066	10109	101	10008	0	100	10021	300	249769	10100	200	10006	200	30012	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10004	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  sha512su1 v0.2d, v1.2d, v0.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10006	200	30018	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	249769	10100	200	10004	200	30012	1	10000	100
10205	20066	10109	101	10008	100	10021	300	249769	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10004	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	249769	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha512su1 v0.2d, v8.2d, v9.2d
  movi v1.16b, 0
  sha512su1 v1.2d, v8.2d, v9.2d
  movi v2.16b, 0
  sha512su1 v2.2d, v8.2d, v9.2d
  movi v3.16b, 0
  sha512su1 v3.2d, v8.2d, v9.2d
  movi v4.16b, 0
  sha512su1 v4.2d, v8.2d, v9.2d
  movi v5.16b, 0
  sha512su1 v5.2d, v8.2d, v9.2d
  movi v6.16b, 0
  sha512su1 v6.2d, v8.2d, v9.2d
  movi v7.16b, 0
  sha512su1 v7.2d, v8.2d, v9.2d

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80108	80101	101	80000	100	80001	300	320010	80102	200	80007	200	240021	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240102	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240018	1	160000	100
160204	80034	80101	101	80000	100	80001	300	320005	80101	200	80006	200	240102	1	160000	100
160204	80116	80101	101	80000	100	80002	300	320010	80102	200	80007	200	240018	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80068	80011	11	80000	0	10	80002	30	320010	80012	20	80007	20	240000	1	160000	10
160024	80038	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160025	80068	80028	11	80017	0	10	80023	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	80034	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 16

Code:

  sha512su1 v0.2d, v16.2d, v17.2d
  sha512su1 v1.2d, v16.2d, v17.2d
  sha512su1 v2.2d, v16.2d, v17.2d
  sha512su1 v3.2d, v16.2d, v17.2d
  sha512su1 v4.2d, v16.2d, v17.2d
  sha512su1 v5.2d, v16.2d, v17.2d
  sha512su1 v6.2d, v16.2d, v17.2d
  sha512su1 v7.2d, v16.2d, v17.2d
  sha512su1 v8.2d, v16.2d, v17.2d
  sha512su1 v9.2d, v16.2d, v17.2d
  sha512su1 v10.2d, v16.2d, v17.2d
  sha512su1 v11.2d, v16.2d, v17.2d
  sha512su1 v12.2d, v16.2d, v17.2d
  sha512su1 v13.2d, v16.2d, v17.2d
  sha512su1 v14.2d, v16.2d, v17.2d
  sha512su1 v15.2d, v16.2d, v17.2d

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	160074	160120	101	160019	100	160025	0	300	0	640014	160103	200	0	160010	200	0	480030	1	0	160000	100
160204	160034	160101	101	160000	100	160001	0	300	0	640005	160101	200	0	160008	200	0	480024	1	0	160000	100
160204	160034	160101	101	160000	100	160001	0	300	0	640005	160101	200	0	160008	200	0	480108	1	0	160000	100
160204	160034	160101	101	160000	100	160001	0	300	0	640005	160101	200	0	160008	200	0	480030	1	0	160000	100
160204	160034	160101	101	160000	100	160001	0	300	0	640005	160101	200	0	160008	200	0	480024	1	0	160000	100
160204	160034	160101	101	160000	100	160001	0	300	0	640005	160101	200	0	160008	200	0	480024	1	0	160000	100
160204	160034	160101	101	160000	100	160001	0	300	0	640096	160125	200	0	160040	200	0	480024	1	0	160000	100
160204	160034	160101	101	160000	100	160001	0	300	0	640005	160101	200	0	160008	200	0	480024	1	0	160000	100
160204	160034	160101	101	160000	100	160001	0	300	0	640005	160101	200	0	160008	200	0	480108	1	0	160000	100
160205	160068	160119	101	160018	100	160024	0	300	0	640005	160101	200	0	160008	200	0	480024	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160025	160068	160028	11	160017	0	10	160023	30	640005	160011	20	160008	20	480000	1	160000	10
160024	160034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	160034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	160034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480159	1	160000	10
160024	160034	160011	11	160000	0	10	160001	30	640000	160010	20	160000	20	480000	1	160000	10
160024	160034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	160034	160011	11	160000	0	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	160275	160131	11	160120	0	10	160125	30	640000	160010	20	160000	20	480000	1	160000	10
163173	178891	163075	2056	160024	995	1872	160029	30	640000	160010	20	160000	20	480000	1	160000	10
160024	160041	160012	11	160001	0	10	160003	30	640014	160013	20	160010	20	480000	1	160000	10

SHA512SU1

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations