Icestorm: SLI (vector, 16B) measurements

Code:

  sli v0.16b, v1.16b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  sli v0.16b, v1.16b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10006	200	20012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509247	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  sli v0.16b, v0.16b, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509580	10134	200	10048	2110	1513	17774	822	670	8845	1139
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10205	20066	10109	101	10008	100	10034	307	509580	10136	202	10046	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	0	20008	1	0	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	202	0	20348	2	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10004	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sli v0.16b, v8.16b, #3
  movi v1.16b, 0
  sli v1.16b, v8.16b, #3
  movi v2.16b, 0
  sli v2.16b, v8.16b, #3
  movi v3.16b, 0
  sli v3.16b, v8.16b, #3
  movi v4.16b, 0
  sli v4.16b, v8.16b, #3
  movi v5.16b, 0
  sli v5.16b, v8.16b, #3
  movi v6.16b, 0
  sli v6.16b, v8.16b, #3
  movi v7.16b, 0
  sli v7.16b, v8.16b, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40449	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160026	1	160000	100
160204	40119	80109	101	80008	100	80012	300	320056	80113	200	80013	200	160026	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160094	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40096	80110	101	80009	100	80013	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43878	80019	11	80008	10	80012	30	320052	80022	20	80012	20	160000	1	160000	10
160024	41234	80011	11	80000	10	80000	30	320196	80058	20	80048	20	160000	1	160000	10
160024	40431	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40394	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40376	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160025	40462	80054	11	80043	10	80049	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40429	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40420	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160025	40522	80055	11	80044	10	80050	30	320000	80010	20	80000	20	160114	1	160000	10
160024	40562	80020	11	80009	10	80013	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  sli v0.16b, v16.16b, #3
  sli v1.16b, v16.16b, #3
  sli v2.16b, v16.16b, #3
  sli v3.16b, v16.16b, #3
  sli v4.16b, v16.16b, #3
  sli v5.16b, v16.16b, #3
  sli v6.16b, v16.16b, #3
  sli v7.16b, v16.16b, #3
  sli v8.16b, v16.16b, #3
  sli v9.16b, v16.16b, #3
  sli v10.16b, v16.16b, #3
  sli v11.16b, v16.16b, #3
  sli v12.16b, v16.16b, #3
  sli v13.16b, v16.16b, #3
  sli v14.16b, v16.16b, #3
  sli v15.16b, v16.16b, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80037	160107	101	160006	100	160010	300	640036	160108	200	160012	200	320028	1	160000	100
160204	80034	160107	101	160006	100	160010	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160107	101	160006	100	160010	300	640044	160110	200	160014	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80108	160017	11	160006	10	160010	30	640036	160018	20	160012	20	320028	1	160000	10
160024	80044	160015	11	160004	10	160008	30	640044	160020	20	160014	20	320028	1	160000	10
160024	80034	160017	11	160006	10	160010	30	640044	160020	20	160014	20	320028	1	160000	10
160024	80034	160017	11	160006	10	160010	30	640044	160020	20	160014	20	320028	1	160000	10
160024	80034	160017	11	160006	10	160010	30	640044	160020	20	160014	20	320028	1	160000	10
160024	80034	160017	11	160006	10	160010	30	640044	160020	20	160014	20	320000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10

SLI (vector, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations