Icestorm: SLI (vector, 2S) measurements

Code:

  sli v0.2s, v1.2s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  sli v0.2s, v1.2s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10205	20066	10109	101	10008	100	10034	300	509248	10100	200	10006	200	20012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509247	10020	20	10006	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  sli v0.2s, v0.2s, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10006	200	20008	1	10000	100
12194	21999	11817	1205	10008	604	1122	10034	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	0	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	0	70	0	509248	10020	20	0	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sli v0.2s, v8.2s, #3
  movi v1.16b, 0
  sli v1.2s, v8.2s, #3
  movi v2.16b, 0
  sli v2.2s, v8.2s, #3
  movi v3.16b, 0
  sli v3.2s, v8.2s, #3
  movi v4.16b, 0
  sli v4.2s, v8.2s, #3
  movi v5.16b, 0
  sli v5.2s, v8.2s, #3
  movi v6.16b, 0
  sli v6.2s, v8.2s, #3
  movi v7.16b, 0
  sli v7.2s, v8.2s, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40536	80110	101	80009	100	80013	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40108	80110	101	80009	100	80013	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	202	160094	2	160000	100
160204	40098	80110	101	80009	100	80013	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43875	80019	11	80008	10	80012	30	320000	80010	20	80000	20	160000	1	160000	10
160024	41161	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40407	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40399	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	41750	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40397	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40416	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40420	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40416	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40416	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  sli v0.2s, v16.2s, #3
  sli v1.2s, v16.2s, #3
  sli v2.2s, v16.2s, #3
  sli v3.2s, v16.2s, #3
  sli v4.2s, v16.2s, #3
  sli v5.2s, v16.2s, #3
  sli v6.2s, v16.2s, #3
  sli v7.2s, v16.2s, #3
  sli v8.2s, v16.2s, #3
  sli v9.2s, v16.2s, #3
  sli v10.2s, v16.2s, #3
  sli v11.2s, v16.2s, #3
  sli v12.2s, v16.2s, #3
  sli v13.2s, v16.2s, #3
  sli v14.2s, v16.2s, #3
  sli v15.2s, v16.2s, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80035	160107	101	160006	100	160010	0	300	0	640036	160108	200	0	160012	200	320028	1	160000	100
160204	80034	160107	101	160006	100	160010	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160205	80069	160141	101	160040	100	160052	0	300	0	640044	160110	200	0	160014	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	320024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	80216	160017	11	160006	10	160010	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320120	1	0	160000	10
160024	80043	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320126	1	0	160000	10
160024	80034	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10

SLI (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations