Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SLI (vector, 4S)

Test 1: uops

Code:

  sli v0.4s, v1.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
100420331001110001000000505801034001042200011000
100420331001110001000000502481000001000200011000
100420331001110001000136915080127198519374963351916021052200011000
100420331001110001000000502481000001000200011000
100420331001110001000000502481000001000200011000
100420331001110001000000502481000001000200011000
100420331001110001000000502481000001000200011000
100420331001110001000000502481000001000200011000
100420331001110001000000502481000001000200011000
100420331001110001000000502481000001000200011000

Test 2: Latency 1->1

Code:

  sli v0.4s, v1.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000620020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509564101342001004520020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092481002020100042020000111000010
10024200331002121100002010000705092481002020100002020096111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010

Test 3: Latency 1->2

Code:

  sli v0.4s, v0.4s, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000314511376102482041017220020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000320511284102502061017420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092481002020100042020008111000010
10024200331002121100002010000705092481002020100042020008111000010
10024200331002121100002010000705092481002020100042020008111000010
10024200331002121100002010000705092481002020100042020008111000010
10024200331002121100002010000705092481002020100042020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sli v0.4s, v8.4s, #3
  movi v1.16b, 0
  sli v1.4s, v8.4s, #3
  movi v2.16b, 0
  sli v2.4s, v8.4s, #3
  movi v3.16b, 0
  sli v3.4s, v8.4s, #3
  movi v4.16b, 0
  sli v4.4s, v8.4s, #3
  movi v5.16b, 0
  sli v5.4s, v8.4s, #3
  movi v6.16b, 0
  sli v6.4s, v8.4s, #3
  movi v7.16b, 0
  sli v7.4s, v8.4s, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044053580109101800081008001230032018880146200800462001600241160000100
1602044010780110101800091008001330032005680113200800132001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244379180020118000910800133032005280022208001220160000116000010
1600244122380011118000010800003032000080010208000020160000116000010
1600244044880011118000010800003032000080010208000020160000116000010
1600244041680011118000010800003032000080010208000020160024116000010
1600244061380011118000010800003032000080010208000020160000116000010
1600244042380011118000010800003032000080010208000020160000116000010
1600244037780011118000010800003032000080010208000020160000116000010
1600244037180011118000010800003032000080010208000020160000116000010
1600244042580011118000010800003032000080010208000020160000116000010
1600244042580011118000010800003032000080010208000020160000116000010

Test 5: throughput

Count: 16

Code:

  sli v0.4s, v16.4s, #3
  sli v1.4s, v16.4s, #3
  sli v2.4s, v16.4s, #3
  sli v3.4s, v16.4s, #3
  sli v4.4s, v16.4s, #3
  sli v5.4s, v16.4s, #3
  sli v6.4s, v16.4s, #3
  sli v7.4s, v16.4s, #3
  sli v8.4s, v16.4s, #3
  sli v9.4s, v16.4s, #3
  sli v10.4s, v16.4s, #3
  sli v11.4s, v16.4s, #3
  sli v12.4s, v16.4s, #3
  sli v13.4s, v16.4s, #3
  sli v14.4s, v16.4s, #3
  sli v15.4s, v16.4s, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800781601051011600041001600083006400441601102001600142003200281160000100
160204800341601071011600061001600103006400361601082001600122003200241160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100
160204800341601051011600041001600083006402081601542001600632003200241160000100
160206801021601751011600741001600943006400441601102001600142003200281160000100
160204800531601051011600041001600083006400361601082001600122003200241160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024801591600171116000610160010306400001600102016000020320000116000010
160024800501600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800391600111116000010160000306401961600612016006120320028116000010
160024800361600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010