Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SLI (vector, 8B)

Test 1: uops

Code:

  sli v0.8b, v1.8b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1005206610091100810345024810001000200011000
1004203310011100010005024810001000200011000

Test 2: Latency 1->1

Code:

  sli v0.8b, v1.8b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000620020012110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092471002020100062020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010

Test 3: Latency 1->2

Code:

  sli v0.8b, v0.8b, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000307509580101362021004620020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000307509580101362021004620020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020088111000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sli v0.8b, v8.8b, #3
  movi v1.16b, 0
  sli v1.8b, v8.8b, #3
  movi v2.16b, 0
  sli v2.8b, v8.8b, #3
  movi v3.16b, 0
  sli v3.8b, v8.8b, #3
  movi v4.16b, 0
  sli v4.8b, v8.8b, #3
  movi v5.16b, 0
  sli v5.8b, v8.8b, #3
  movi v6.16b, 0
  sli v6.8b, v8.8b, #3
  movi v7.16b, 0
  sli v7.8b, v8.8b, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044048780110101800091008001330032005280112200800122001600241160000100
1602044010880110101800091008001330032005280112200800122001600241160000100
1602044009980110101800091008001330032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044010880110101800091008001330032005280112200800122001600261160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5057

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244408880019118000810800123032005680023208001320160000116000010
1600244134180011118000010800003032000080010208000020160000116000010
1600244043480011118000010800003032000080010208000020160000116000010
1600244043480011118000010800003032000080010208000020160000116000010
1600244045680011118000010800003032000080010208000020160000116000010
1600244043180011118000010800003032000080010208000020160000116000010
1600244045280011118000010800003032000080010208000020160000116000010
1600244045280011118000010800003032000080010208000020160000116000010
1600244041380011118000010800003032000080010208000020160000116000010
1600244045280011118000010800003032000080010208000020160000116000010

Test 5: throughput

Count: 16

Code:

  sli v0.8b, v16.8b, #3
  sli v1.8b, v16.8b, #3
  sli v2.8b, v16.8b, #3
  sli v3.8b, v16.8b, #3
  sli v4.8b, v16.8b, #3
  sli v5.8b, v16.8b, #3
  sli v6.8b, v16.8b, #3
  sli v7.8b, v16.8b, #3
  sli v8.8b, v16.8b, #3
  sli v9.8b, v16.8b, #3
  sli v10.8b, v16.8b, #3
  sli v11.8b, v16.8b, #3
  sli v12.8b, v16.8b, #3
  sli v13.8b, v16.8b, #3
  sli v14.8b, v16.8b, #3
  sli v15.8b, v16.8b, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800831601051011600041001600080300064004416011020001600142003200241160000100
160204800341601071011600061001600100300064020816015420001600642003200241160000100
160204800341601051011600041001600080300064003616010820001600122003200241160000100
160204800341601051011600041001600080300064003616010820001600122003200241160000100
160204800341601051011600041001600080300064003616010820001600122003200241160000100
160204800341601051011600041001600080300064003616010820001600122003200281160000100
160204800341601051011600041001600080300064003616010820001600122003200241160000100
160204800341601051011600041001600080300064003616010820001600122003200241160000100
160204800341601051011600041001600080300064003616010820001600122003200241160000100
160204800341601051011600041001600080300064003616010820001600122003200241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024802681600151116000410160008306400361600182016001220320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306402081600642016006120320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010