Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMAXV (vector, 8H)

Test 1: uops

Code:

  smaxv h0, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007658910621082200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->2

Code:

  smaxv h0, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620020012110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430084101091011000810010033300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000707689051002020100002020000111000010
100243003310021211000002010000707692471005120100442020000111000010

Test 3: throughput

Count: 8

Code:

  smaxv h0, v8.8h
  smaxv h1, v8.8h
  smaxv h2, v8.8h
  smaxv h3, v8.8h
  smaxv h4, v8.8h
  smaxv h5, v8.8h
  smaxv h6, v8.8h
  smaxv h7, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80204400418010710180006100800103003200368010820080012200160028180000100
80204400358010710180006100800103003200368010820080012200160024180000100
80204400358010710180006100800103003200448011020080014200160024180000100
80204400448010510180004100800083003200368010820080012200160024180000100
80204400358010510180004100800083003200368010820080012200160024180000100
80204400358010510180004100800083003200368010820080012200160024180000100
80204400358010510180004100800083003200368010820080012200160024180000100
80204400358010510180004100800083003200368010820080012200160024180000100
80204400358010510180004100800083003200368010820080012200160024180000100
80204400358010510180004100800083003200368010820080012200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
800244012280027218000620800107032000080020208000020160000118000010
800244003580021218000020800007032000080020208000020160000118000010
800244003580021218000020800007032000080020208000020160000118000010
800244003580021218000020800007032000080020208000020160000118000010
800244003580021218000020800007032000080020208000020160000118000010
800244003580021218000020800007032000080020208000020160000118000010
800244032980218218019720801977032000080020208000020160000118000010
800244003580021218000020800007032020880074208006620160000118000010
800244003580021218000020800007032000080020208000020160396118000010
800244003580021218000020800007032000080020208000020160000118000010