Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMLAL2 (vector, 2D)

Test 1: uops

Code:

  smlal2 v0.2d, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000

Test 2: Latency 1->1

Code:

  smlal2 v0.2d, v1.4s, v2.4s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10025300661002721100062010031707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 3: Latency 1->2

Code:

  smlal2 v0.2d, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
102043003310101101100001001000030076890510100200100062000300181010000100
102043003310101101100001001000030076890510100200100042000300121010000100
102043003310101101100001001000030076890510100200100062000300181010000100
102043003310101101100001001000030076890510100200100042000300121010000100
102043003310101101100001001000030076890510100200100042000300121010000100
102043003310101101100001001000030076890510100200100042000300121010000100
102043003310101101100001001000030076890510100200100042000300121010000100
102043003310101101100001001000030076890510100200100042000300121010000100
102043003310101101100001001000030076890510100200100042000300121010000100
102043003310101101100001001000030076890510100200100042000300121010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100062030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300841002921100082010033707689051002020100002030000111000010
10024300331002121100002010000667705431011920101192030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707710891015220101582030138111000010
10024300331002121100002010000707689051002020100002030012111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 4: Latency 1->3

Code:

  smlal2 v0.2d, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000307769247101332021004420030018110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000620030018110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020530066101071011000610010031300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030132111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  smlal2 v0.2d, v8.4s, v9.4s
  movi v1.16b, 0
  smlal2 v1.2d, v8.4s, v9.4s
  movi v2.16b, 0
  smlal2 v2.2d, v8.4s, v9.4s
  movi v3.16b, 0
  smlal2 v3.2d, v8.4s, v9.4s
  movi v4.16b, 0
  smlal2 v4.2d, v8.4s, v9.4s
  movi v5.16b, 0
  smlal2 v5.2d, v8.4s, v9.4s
  movi v6.16b, 0
  smlal2 v6.2d, v8.4s, v9.4s
  movi v7.16b, 0
  smlal2 v7.2d, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044047780109101800081008001230032005680113200800132002400361160000100
1602044011280110101800091008001330032005280112200800122002400361160000100
1602044008680109101800081008001230032005680113200800132002400391160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032019680148200800482002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5054

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244398080020118000910800133032005680023208001320240039116000010
1600244121780011118000010800003032000080010208000020240000116000010
1600244039780011118000010800003032000080010208000020240000116000010
1600254229580054118004310800473032000080010208000020240000116000010
1600244045280011118000010800003032000080010208000020240000116000010
1600244043680011118000010800003032000080010208000020240000116000010
1600244041980011118000010800003032000080010208000020240000116000010
1600244043680011118000010800003032000080010208000020240000116000010
1600244044980011118000010800003032000080010208000020240000116000010
1600244044080011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  smlal2 v0.2d, v16.4s, v17.4s
  smlal2 v1.2d, v16.4s, v17.4s
  smlal2 v2.2d, v16.4s, v17.4s
  smlal2 v3.2d, v16.4s, v17.4s
  smlal2 v4.2d, v16.4s, v17.4s
  smlal2 v5.2d, v16.4s, v17.4s
  smlal2 v6.2d, v16.4s, v17.4s
  smlal2 v7.2d, v16.4s, v17.4s
  smlal2 v8.2d, v16.4s, v17.4s
  smlal2 v9.2d, v16.4s, v17.4s
  smlal2 v10.2d, v16.4s, v17.4s
  smlal2 v11.2d, v16.4s, v17.4s
  smlal2 v12.2d, v16.4s, v17.4s
  smlal2 v13.2d, v16.4s, v17.4s
  smlal2 v14.2d, v16.4s, v17.4s
  smlal2 v15.2d, v16.4s, v17.4s
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204801091601051011600041001600083006400441601102001600142004800391160000100
160204800351601071011600061001600103006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160205800711601441011600431001600553006400361601082001600122004800391160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800391160000100
160204800351601071011600061001600103006400361601082001600122004800361160000100
160204800451601071011600061001600103006400361601082001600122004800361160000100
160204800351601071011600061001600103006400361601082001600122004800361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024802161600171116000610160010030064000016001020016000020480000116000010
160024800361600111116000010160000030064000016001020016000020480000116000010
160024800351600111116000010160000030064000016001020016000020480000116000010
160024800351600111116000010160000030064020816006420016006020480000116000010
160024800351600111116000010160000030064000016001020016000020480000116000010
160024800351600111116000010160000030064000016001020016000020480000116000010
160024800351600111116000010160000030064000016001020016000020480000116000010
160024800351600111116000010160000030064000016001020016000020480000116000010
160024800351600111116000010160000030064000016001020016000020480000116000010
160024800351600111116000010160000030064000016001020016000020480000116000010