Icestorm: SMLAL2 (vector, 2D) measurements

Code:

  smlal2 v0.2d, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  smlal2 v0.2d, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10025	30066	10027	21	10006	20	10031	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  smlal2 v0.2d, v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	0	30018	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	0	30018	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10006	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30084	10029	21	10008	20	10033	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	66	770543	10119	20	10119	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	771089	10152	20	10158	20	30138	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30012	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  smlal2 v0.2d, v1.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	307	769247	10133	202	10044	200	30018	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	30018	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10205	30066	10107	101	10006	100	10031	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30132	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	0	70	0	768905	10020	20	0	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  smlal2 v0.2d, v8.4s, v9.4s
  movi v1.16b, 0
  smlal2 v1.2d, v8.4s, v9.4s
  movi v2.16b, 0
  smlal2 v2.2d, v8.4s, v9.4s
  movi v3.16b, 0
  smlal2 v3.2d, v8.4s, v9.4s
  movi v4.16b, 0
  smlal2 v4.2d, v8.4s, v9.4s
  movi v5.16b, 0
  smlal2 v5.2d, v8.4s, v9.4s
  movi v6.16b, 0
  smlal2 v6.2d, v8.4s, v9.4s
  movi v7.16b, 0
  smlal2 v7.2d, v8.4s, v9.4s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40477	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240036	1	160000	100
160204	40112	80110	101	80009	100	80013	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240039	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320196	80148	200	80048	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5054

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43980	80020	11	80009	10	80013	30	320056	80023	20	80013	20	240039	1	160000	10
160024	41217	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40397	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160025	42295	80054	11	80043	10	80047	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40452	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40436	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40419	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40436	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40449	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40440	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 16

Code:

  smlal2 v0.2d, v16.4s, v17.4s
  smlal2 v1.2d, v16.4s, v17.4s
  smlal2 v2.2d, v16.4s, v17.4s
  smlal2 v3.2d, v16.4s, v17.4s
  smlal2 v4.2d, v16.4s, v17.4s
  smlal2 v5.2d, v16.4s, v17.4s
  smlal2 v6.2d, v16.4s, v17.4s
  smlal2 v7.2d, v16.4s, v17.4s
  smlal2 v8.2d, v16.4s, v17.4s
  smlal2 v9.2d, v16.4s, v17.4s
  smlal2 v10.2d, v16.4s, v17.4s
  smlal2 v11.2d, v16.4s, v17.4s
  smlal2 v12.2d, v16.4s, v17.4s
  smlal2 v13.2d, v16.4s, v17.4s
  smlal2 v14.2d, v16.4s, v17.4s
  smlal2 v15.2d, v16.4s, v17.4s

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80109	160105	101	160004	100	160008	300	640044	160110	200	160014	200	480039	1	160000	100
160204	80035	160107	101	160006	100	160010	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160205	80071	160144	101	160043	100	160055	300	640036	160108	200	160012	200	480039	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480039	1	160000	100
160204	80035	160107	101	160006	100	160010	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80045	160107	101	160006	100	160010	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160107	101	160006	100	160010	300	640036	160108	200	160012	200	480036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80216	160017	11	160006	10	160010	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640208	160064	20	0	160060	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	480000	1	160000	10

SMLAL2 (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations