Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMLAL2 (vector, 4S)

Test 1: uops

Code:

  smlal2 v0.4s, v1.8h, v2.8h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000

Test 2: Latency 1->1

Code:

  smlal2 v0.4s, v1.8h, v2.8h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020530066101071011000610010031300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010

Test 3: Latency 1->2

Code:

  smlal2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620030018110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030468111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 4: Latency 1->3

Code:

  smlal2 v0.4s, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620030018110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000307769247101332021004620030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1002430033100212110000201000070769247100512010044200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200301231101000010
100243003310021211000020100006676924710051201004765484376213302868228870683668
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  smlal2 v0.4s, v8.8h, v9.8h
  movi v1.16b, 0
  smlal2 v1.4s, v8.8h, v9.8h
  movi v2.16b, 0
  smlal2 v2.4s, v8.8h, v9.8h
  movi v3.16b, 0
  smlal2 v3.4s, v8.8h, v9.8h
  movi v4.16b, 0
  smlal2 v4.4s, v8.8h, v9.8h
  movi v5.16b, 0
  smlal2 v5.4s, v8.8h, v9.8h
  movi v6.16b, 0
  smlal2 v6.4s, v8.8h, v9.8h
  movi v7.16b, 0
  smlal2 v7.4s, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044048880109101800081008001230032005680113200800132002400361160000100
1602044010880110101800091008001330032005280112200800122002400361160000100
1602044010180110101800091008001330032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5051

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244384280019118000810800123032005680023208001320240000116000010
1600244116880011118000010800003032000080010208000020240000116000010
1600244038980011118000010800003032000080010208000020240000116000010
1600244035680011118000010800003032000080010208000020240000116000010
1600244042280011118000010800003032000080010208000020240000116000010
1600244043880011118000010800003032000080010208000020240000116000010
1600244040980011118000010800003032000080010208000020240000116000010
1600244039180011118000010800003032000080010208000020240000116000010
1600244038280011118000010800003032000080010208000020240000116000010
1600244040080011118000010800003032020080059208004920240000116000010

Test 6: throughput

Count: 16

Code:

  smlal2 v0.4s, v16.8h, v17.8h
  smlal2 v1.4s, v16.8h, v17.8h
  smlal2 v2.4s, v16.8h, v17.8h
  smlal2 v3.4s, v16.8h, v17.8h
  smlal2 v4.4s, v16.8h, v17.8h
  smlal2 v5.4s, v16.8h, v17.8h
  smlal2 v6.4s, v16.8h, v17.8h
  smlal2 v7.4s, v16.8h, v17.8h
  smlal2 v8.4s, v16.8h, v17.8h
  smlal2 v9.4s, v16.8h, v17.8h
  smlal2 v10.4s, v16.8h, v17.8h
  smlal2 v11.4s, v16.8h, v17.8h
  smlal2 v12.4s, v16.8h, v17.8h
  smlal2 v13.4s, v16.8h, v17.8h
  smlal2 v14.4s, v16.8h, v17.8h
  smlal2 v15.4s, v16.8h, v17.8h
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204801201601071011600061001600103006400441601102001600142004800421160000100
160204800451601071011600061001600103006400441601102001600132004800391160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100
160205800711601421011600411001600533006400441601102001600132004800361160000100
160204800351601051011600041001600083006400361601082001600122004800361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024801721600171116000610160010306400441600202016001420480000116000010
160024800361600111116000010160000306400001600102016000020480000116000010
160026801061600911116008010160100306400441600202016001420480000116000010
160025800711600541116004310160055306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010