Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMLAL2 (vector, 8H)

Test 1: uops

Code:

  smlal2 v0.8h, v1.16b, v2.16b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000

Test 2: Latency 1->1

Code:

  smlal2 v0.8h, v1.16b, v2.16b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420030012110000100
1020530066101091031000610210031300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420630486410000100
1020530066101071011000610010031300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420230138210000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020530066101091031000610210031300768905101002001000420030018110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10025300661002721100062010031707689051002020100042030012111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 3: Latency 1->2

Code:

  smlal2 v0.8h, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000030007689051010020001000620030018110000100
1020430033101011011000010010000030007689051010020001000620030012110000100
1020430084101091011000810010033030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007694511013320001004420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030000111000010
100243003310021211000002010000707689051002020100002030012111000010
100243003310021211000002010000707689051002020100002030000111000010

Test 4: Latency 1->3

Code:

  smlal2 v0.8h, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000030007689051010020001000620030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007692471013120001004820030012110000100
10204300331010110110000100100001555631091858076812614411386918371005820030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100
1020430033101011011000010010000030007689051010020001000520030012110000100
1020430033101011011000010010000030007689051010020001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100062030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10025300661002721100062010031707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  smlal2 v0.8h, v8.16b, v9.16b
  movi v1.16b, 0
  smlal2 v1.8h, v8.16b, v9.16b
  movi v2.16b, 0
  smlal2 v2.8h, v8.16b, v9.16b
  movi v3.16b, 0
  smlal2 v3.8h, v8.16b, v9.16b
  movi v4.16b, 0
  smlal2 v4.8h, v8.16b, v9.16b
  movi v5.16b, 0
  smlal2 v5.8h, v8.16b, v9.16b
  movi v6.16b, 0
  smlal2 v6.8h, v8.16b, v9.16b
  movi v7.16b, 0
  smlal2 v7.8h, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044054280109101800081008001230032005680113200800132002400391160000100
1602044009680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244384480020118000910800133032019280057208004720240039116000010
1600244127180011118000010800003032000080010208000020240000116000010
1600244042380011118000010800003032000080010208000020240000116000010
1600244042380011118000010800003032005680023208001320240000116000010
1600244052280011118000010800003032000080010208000020240000116000010
1600244039880011118000010800003032000080010208000020240000116000010
1600244040080011118000010800003032000080010208000020240000116000010
1600244050780011118000010800003032000080010208000020240000116000010
1600244042980011118000010800003032000080010208000020240000116000010
1600244046380011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  smlal2 v0.8h, v16.16b, v17.16b
  smlal2 v1.8h, v16.16b, v17.16b
  smlal2 v2.8h, v16.16b, v17.16b
  smlal2 v3.8h, v16.16b, v17.16b
  smlal2 v4.8h, v16.16b, v17.16b
  smlal2 v5.8h, v16.16b, v17.16b
  smlal2 v6.8h, v16.16b, v17.16b
  smlal2 v7.8h, v16.16b, v17.16b
  smlal2 v8.8h, v16.16b, v17.16b
  smlal2 v9.8h, v16.16b, v17.16b
  smlal2 v10.8h, v16.16b, v17.16b
  smlal2 v11.8h, v16.16b, v17.16b
  smlal2 v12.8h, v16.16b, v17.16b
  smlal2 v13.8h, v16.16b, v17.16b
  smlal2 v14.8h, v16.16b, v17.16b
  smlal2 v15.8h, v16.16b, v17.16b
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800851601051011600041001600080300064004416011020001600142004800421160000100
160204800351601071011600061001600100300064003616010820001600122004800361160000100
160204800351601051011600041001600080300064003616010820001600122004800361160000100
160204800351601051011600041001600080300064003616010820001600122004800361160000100
160204800351601051011600041001600080300064004416011020001600132004800391160000100
160204800351601051011600041001600080300064003616010820001600122004800361160000100
160204800351601051011600041001600080300064003616010820001600122004800361160000100
160204800351601051011600041001600080300064003616010820001600122004800361160000100
160204800351601051011600041001600080300064003616010820001600122004801801160000100
160204800351601051011600041001600080300064003616010820001600122004800391160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600248026416001511160004010160008306400441600202016001420480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480195116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480195116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
207339230498201291249101603451603624005160343306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010
1600248003516001111160000010160000306400001600102016000020480000116000010