Icestorm: SMLAL (vector, 4S) measurements

Code:

  smlal v0.4s, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  smlal v0.4s, v1.4h, v2.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	769247	10051	20	10044	20	0	30000	11	0	10000	10

Test 3: Latency 1->2

Code:

  smlal v0.4s, v0.4h, v1.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	30018	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30083	10109	101	10008	100	10033	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30135	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  smlal v0.4s, v1.4h, v0.4h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	30018	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10006	20	30018	11	10000	10
10958	37249	11143	689	10009	445	699	10036	70	768905	10020	20	10004	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  smlal v0.4s, v8.4h, v9.4h
  movi v1.16b, 0
  smlal v1.4s, v8.4h, v9.4h
  movi v2.16b, 0
  smlal v2.4s, v8.4h, v9.4h
  movi v3.16b, 0
  smlal v3.4s, v8.4h, v9.4h
  movi v4.16b, 0
  smlal v4.4s, v8.4h, v9.4h
  movi v5.16b, 0
  smlal v5.4s, v8.4h, v9.4h
  movi v6.16b, 0
  smlal v6.4s, v8.4h, v9.4h
  movi v7.16b, 0
  smlal v7.4s, v8.4h, v9.4h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40537	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240039	1	160000	100
160204	40096	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320196	80148	200	80048	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5056

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	44026	80019	11	80008	10	80012	30	320056	80023	20	80013	20	240000	1	160000	10
160024	41281	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240036	1	160000	10
160024	40500	80011	11	80000	10	80000	30	320056	80023	20	80013	20	240000	1	160000	10
160024	43827	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40472	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40440	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40462	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40446	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160025	40577	80057	11	80046	10	80050	30	320332	80092	20	80082	20	240000	1	160000	10
160024	40567	80046	11	80035	10	80035	30	320000	80010	20	80000	20	240141	1	160000	10

Test 6: throughput

Count: 16

Code:

  smlal v0.4s, v16.4h, v17.4h
  smlal v1.4s, v16.4h, v17.4h
  smlal v2.4s, v16.4h, v17.4h
  smlal v3.4s, v16.4h, v17.4h
  smlal v4.4s, v16.4h, v17.4h
  smlal v5.4s, v16.4h, v17.4h
  smlal v6.4s, v16.4h, v17.4h
  smlal v7.4s, v16.4h, v17.4h
  smlal v8.4s, v16.4h, v17.4h
  smlal v9.4s, v16.4h, v17.4h
  smlal v10.4s, v16.4h, v17.4h
  smlal v11.4s, v16.4h, v17.4h
  smlal v12.4s, v16.4h, v17.4h
  smlal v13.4s, v16.4h, v17.4h
  smlal v14.4s, v16.4h, v17.4h
  smlal v15.4s, v16.4h, v17.4h

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80086	160107	101	160006	100	160010	300	640044	160110	200	160014	200	480039	1	160000	100
160204	80045	160107	101	160006	100	160010	300	640036	160108	200	160012	200	480195	1	160000	100
160204	80045	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480039	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80054	160107	101	160006	100	160010	300	640044	160110	200	160014	200	480042	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80175	160015	11	160004	10	160008	30	640044	160020	20	160014	20	480000	1	160000	10
160024	80036	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160025	80071	160055	11	160044	10	160056	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10

SMLAL (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations