Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMLSL2 (by element, 4S)

Test 1: uops

Code:

  smlsl2 v0.4s, v1.8h, v2.h[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000

Test 2: Latency 1->1

Code:

  smlsl2 v0.4s, v1.8h, v2.h[1]
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042030012111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030144111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 3: Latency 1->2

Code:

  smlsl2 v0.4s, v0.8h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620030018110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000677692471005120100462030012111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 4: Latency 1->3

Code:

  smlsl2 v0.4s, v1.8h, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204300331010110110000010010000300768905101002001000620030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
10024300331002121100000201000070768905100202010000200300001101000010
10024300331002121100000201000070768905100202010000200300001101000010
10024300331002121100000201000070768905100202010000200300001101000010
10024300331002121100000201000070768905100202010000200300001101000010
10024300331002121100000201000070768905100202010000200301291101000010
10024300331002121100000201000070768905100202010000200300001101000010
10024300331002121100000201000070768905100202010000200300001101000010
10024300331002121100000201000070768905100202010000200300001101000010
10024300331002121100000201000070768905100202010000200300001101000010
10024300331002121100000201000070768905100202010000200300001101000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  smlsl2 v0.4s, v8.8h, v9.h[1]
  movi v1.16b, 0
  smlsl2 v1.4s, v8.8h, v9.h[1]
  movi v2.16b, 0
  smlsl2 v2.4s, v8.8h, v9.h[1]
  movi v3.16b, 0
  smlsl2 v3.4s, v8.8h, v9.h[1]
  movi v4.16b, 0
  smlsl2 v4.4s, v8.8h, v9.h[1]
  movi v5.16b, 0
  smlsl2 v5.4s, v8.8h, v9.h[1]
  movi v6.16b, 0
  smlsl2 v6.4s, v8.8h, v9.h[1]
  movi v7.16b, 0
  smlsl2 v7.4s, v8.8h, v9.h[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044045580110101800091008001330032005680113200800132002400391160000100
1602044010880110101800091008001330032005280112200800122002400361160000100
1602044008680109101800081008001230032020480150200800502002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244386380019118000810800123032005680023208001320240000116000010
1600244125280011118000010800003032000080010208000020240000116000010
1600244039780011118000010800003032000080010208000020240000116000010
1600244164280011118000010800003032000080010208000020240000116000010
1600244043480011118000010800003032000080010208000020240000116000010
1600244043580011118000010800003032000080010208000020240000116000010
1600244042480011118000010800003032019680058208004820240000116000010
1600244049780011118000010800003032000080010208000020240000116000010
1600244043780011118000010800003032000080010208000020240000116000010
1600244043680011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 12

Code:

  smlsl2 v0.4s, v12.8h, v13.h[1]
  smlsl2 v1.4s, v12.8h, v13.h[1]
  smlsl2 v2.4s, v12.8h, v13.h[1]
  smlsl2 v3.4s, v12.8h, v13.h[1]
  smlsl2 v4.4s, v12.8h, v13.h[1]
  smlsl2 v5.4s, v12.8h, v13.h[1]
  smlsl2 v6.4s, v12.8h, v13.h[1]
  smlsl2 v7.4s, v12.8h, v13.h[1]
  smlsl2 v8.4s, v12.8h, v13.h[1]
  smlsl2 v9.4s, v12.8h, v13.h[1]
  smlsl2 v10.4s, v12.8h, v13.h[1]
  smlsl2 v11.4s, v12.8h, v13.h[1]
  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
120204600751201071011200061001200103004800441201102001200142003600421120000100
120204600351201071011200061001200103004800441201102001200132003600361120000100
120204600351201051011200041001200083004800361201082001200122003600361120000100
120204600351201051011200041001200083004800361201082001200122003600361120000100
120204600351201051011200041001200083004800361201082001200122003600361120000100
120204600351201051011200041001200083004800361201082001200122003600361120000100
120204600351201051011200041001200083004800361201082001200122003600361120000100
120204600351201051011200041001200083004800361201082001200122003600361120000100
120204600351201051011200041001200083004800361201082001200122003600361120000100
120204600351201051011200041001200083004803801202002001201132003600361120000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5003

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
120024601811200151112000410120008304800441200202012001420360000112000010
120024600351200111112000010120000304800001200102012000020360000112000010
120024600351200111112000010120000304800001200102012000020360000112000010
120024600351200111112000010120000304800001200102012000020360000112000010
120024600351200111112000010120000304800001200102012000020360000112000010
120024600351200111112000010120000304800001200102012000020360000112000010
120024600351200111112000010120000304800001200102012000020360000112000010
120024600351200111112000010120000304800001200102012000020360000112000010
120024600351200111112000010120000304800001200102012000020360000112000010
120024600351200111112000010120000304800001200102012000020360000112000010