Icestorm: SMLSL2 (vector, 4S) measurements

Code:

  smlsl2 v0.4s, v1.8h, v2.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3102	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3123	1	1000

Test 2: Latency 1->1

Code:

  smlsl2 v0.4s, v1.8h, v2.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  smlsl2 v0.4s, v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30236	10135	103	10032	102	10132	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	69	769247	10051	20	10048	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  smlsl2 v0.4s, v1.8h, v0.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10006	200	30018	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10006	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30018	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
12158	40899	11796	1157	10008	631	1086	10033	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  smlsl2 v0.4s, v8.8h, v9.8h
  movi v1.16b, 0
  smlsl2 v1.4s, v8.8h, v9.8h
  movi v2.16b, 0
  smlsl2 v2.4s, v8.8h, v9.8h
  movi v3.16b, 0
  smlsl2 v3.4s, v8.8h, v9.8h
  movi v4.16b, 0
  smlsl2 v4.4s, v8.8h, v9.8h
  movi v5.16b, 0
  smlsl2 v5.4s, v8.8h, v9.8h
  movi v6.16b, 0
  smlsl2 v6.4s, v8.8h, v9.8h
  movi v7.16b, 0
  smlsl2 v7.4s, v8.8h, v9.8h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40923	80286	101	80185	100	80189	300	320772	80292	200	80192	200	240666	1	160000	100
160204	40594	80283	101	80182	100	80186	300	320784	80295	200	80195	200	240459	1	160000	100
160204	40476	80254	101	80153	100	80157	300	320472	80217	200	80117	200	240444	1	160000	100
160204	40523	80287	101	80186	100	80190	306	320488	80223	202	80121	200	240468	1	160000	100
160204	40471	80248	101	80147	100	80151	300	320612	80252	200	80152	200	240570	1	160000	100
160204	40559	80282	101	80181	100	80185	300	320604	80250	200	80150	200	240555	1	160000	100
160204	40502	80251	101	80150	100	80154	300	320636	80258	200	80158	202	240462	2	160000	100
160204	40086	80109	101	80008	100	80012	300	320200	80149	200	80049	200	240036	1	160000	100
160205	40131	80145	101	80044	100	80048	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43908	80020	11	80009	10	80013	30	320056	80023	20	80013	20	240000	1	160000	10
160024	44448	80020	11	80009	10	80013	30	320056	80023	20	80013	20	240039	1	160000	10
160024	40469	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40439	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40407	80011	11	80000	10	80000	30	320204	80060	20	80050	20	240000	1	160000	10
160024	40438	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40438	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40428	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40398	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40399	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 16

Code:

  smlsl2 v0.4s, v16.8h, v17.8h
  smlsl2 v1.4s, v16.8h, v17.8h
  smlsl2 v2.4s, v16.8h, v17.8h
  smlsl2 v3.4s, v16.8h, v17.8h
  smlsl2 v4.4s, v16.8h, v17.8h
  smlsl2 v5.4s, v16.8h, v17.8h
  smlsl2 v6.4s, v16.8h, v17.8h
  smlsl2 v7.4s, v16.8h, v17.8h
  smlsl2 v8.4s, v16.8h, v17.8h
  smlsl2 v9.4s, v16.8h, v17.8h
  smlsl2 v10.4s, v16.8h, v17.8h
  smlsl2 v11.4s, v16.8h, v17.8h
  smlsl2 v12.4s, v16.8h, v17.8h
  smlsl2 v13.4s, v16.8h, v17.8h
  smlsl2 v14.4s, v16.8h, v17.8h
  smlsl2 v15.4s, v16.8h, v17.8h

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80093	160107	101	160006	100	160010	300	640044	160110	200	160014	200	480042	1	160000	100
160204	80045	160107	101	160006	100	160010	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480198	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	80154	160015	11	160004	10	160008	0	30	0	640044	160020	20	0	160014	20	0	480183	1	0	160000	10
160025	80148	160056	11	160045	10	160057	0	30	0	640044	160020	20	0	160014	20	0	480042	1	0	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	480000	1	0	160000	10
160024	80036	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	480000	1	0	160000	10
160024	80036	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	480000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	480000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	480189	1	0	160000	10
160024	80072	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	480000	1	0	160000	10
160024	80050	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	480000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	0	480000	1	0	160000	10

SMLSL2 (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations