Icestorm: SMOV (H to X) measurements

Code:

  smov x0, v0.h[1]

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000
1004	1034	2001	1001	1000	1000	4000	1000	1000	1000	1001	1000

Test 2: Latency 1->2 roundtrip

Code:

  smov x0, v0.h[1]
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0032

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1245700	899368	20100	200	10003	10003	200	10003	10003	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10021	300	1226040	899505	20136	200	10026	10026	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70032	30101	10101	10000	10000	100	10000	10000	300	1248868	899368	20100	200	10002	10002	200	10002	10002	10001	10000	10100
20204	70188	30101	10101	10000	10000	100	10000	10000	300	1249444	899784	20100	200	10002	10002	200	10002	10002	10001	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0032

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	70033	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70035	30011	10011	10000	10000	10	10000	10084	30	1223926	902660	20154	20	10086	10085	20	10000	10000	10001	10000	10010
20024	70039	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10023	10022	10004	10000	10010
20024	70579	30056	10026	10015	10015	10	10075	10105	30	1231928	904458	20190	20	10107	10106	20	10107	10106	10016	10000	10010
20024	70472	30047	10023	10012	10012	10	10060	10105	30	1226692	904380	20190	20	10107	10106	20	10023	10022	10004	10000	10010
20024	70032	30011	10011	10000	10000	10	10000	10000	30	1248868	899368	20010	20	10000	10000	20	10000	10000	10001	10000	10010

Test 3: throughput

Count: 8

Code:

  smov x0, v8.h[1]
  smov x1, v8.h[1]
  smov x2, v8.h[1]
  smov x3, v8.h[1]
  smov x4, v8.h[1]
  smov x5, v8.h[1]
  smov x6, v8.h[1]
  smov x7, v8.h[1]

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
80205	80068	160132	80115	80017	100	80022	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80205	80068	160132	80115	80017	100	80022	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100
80204	80034	160101	80101	80000	100	80001	300	320005	80101	200	80008	200	80008	80001	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
80024	80041	160023	80021	80002	20	80004	70	320000	80020	20	80000	20	80000	80011	80010
80024	80034	160021	80021	80000	20	80000	70	320000	80020	20	80000	20	80000	80011	80010
80024	80034	160021	80021	80000	20	80000	70	320000	80020	20	80000	20	80000	80011	80010
80024	80034	160021	80021	80000	20	80000	70	320101	80045	20	80028	20	80000	80011	80010
80024	80034	160021	80021	80000	20	80000	70	320000	80020	20	80000	20	80034	80025	80010
80024	80329	160297	80153	80144	20	80150	70	320000	80020	20	80000	20	80026	80033	80010
80024	80034	160021	80021	80000	20	80000	70	320000	80020	20	80000	20	80000	80011	80010
80024	80034	160021	80021	80000	20	80000	70	320909	80245	20	80242	20	80220	80187	80010
80024	80325	160067	80043	80024	20	80025	70	320101	80045	20	80026	20	80000	80011	80010
80024	80034	160021	80021	80000	20	80000	70	320000	80020	20	80000	20	80000	80011	80010

SMOV (H to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations