Icestorm: SQDMLAL2 (vector, 2D) measurements

Code:

  sqdmlal2 v0.2d, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  sqdmlal2 v0.2d, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	769247	10051	20	10042	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	69	769451	10053	20	10041	20	30123	11	10000	10
10024	30033	10021	21	10000	20	10000	66	771089	10152	20	10158	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  sqdmlal2 v0.2d, v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	30018	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	307	769247	10133	202	10046	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10006	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	66	769232	10051	20	10045	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	69	769247	10051	20	10044	20	30000	11	10000	10
12102	48593	11879	1152	10006	721	1121	10031	70	768905	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  sqdmlal2 v0.2d, v1.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	30018	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	202	30138	2	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10006	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	65	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10025	30066	10027	21	10006	20	10031	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqdmlal2 v0.2d, v8.4s, v9.4s
  movi v1.16b, 0
  sqdmlal2 v1.2d, v8.4s, v9.4s
  movi v2.16b, 0
  sqdmlal2 v2.2d, v8.4s, v9.4s
  movi v3.16b, 0
  sqdmlal2 v3.2d, v8.4s, v9.4s
  movi v4.16b, 0
  sqdmlal2 v4.2d, v8.4s, v9.4s
  movi v5.16b, 0
  sqdmlal2 v5.2d, v8.4s, v9.4s
  movi v6.16b, 0
  sqdmlal2 v6.2d, v8.4s, v9.4s
  movi v7.16b, 0
  sqdmlal2 v7.2d, v8.4s, v9.4s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	40471	80110	101	80009	100	80013	0	300	0	320056	80113	200	0	80013	422	197	240255	78	36	160000	183
160204	40133	80110	101	80009	100	80013	0	300	0	320056	80113	200	0	80013	200	0	240036	1	0	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	0	240036	1	0	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	0	240036	1	0	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	0	240036	1	0	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	0	240036	1	0	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	0	240036	1	0	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	0	240036	1	0	160000	100
160204	40086	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	0	240036	1	0	160000	100
160204	40105	80109	101	80008	100	80012	0	300	0	320052	80112	200	0	80012	200	0	240036	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5054

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160025	44092	80057	11	80046	0	10	80050	0	30	0	320056	80023	20	0	80013	20	240000	1	160000	10
160024	41301	80011	11	80000	0	10	80000	0	30	0	320056	80023	20	0	80013	20	240000	1	160000	10
160024	40426	80011	11	80000	0	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40477	80011	11	80000	0	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
165286	59406	84129	2516	80087	1526	2305	80080	0	30	0	320192	80057	20	0	80047	20	240000	1	160000	10
160024	40437	80011	11	80000	0	10	80000	898	19629	9803	320336	82280	1869	1036	80083	20	240000	1	160000	10
160024	40428	80011	11	80000	0	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40434	80011	11	80000	0	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40437	80011	11	80000	0	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40448	80011	11	80000	0	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10

Test 6: throughput

Count: 16

Code:

  sqdmlal2 v0.2d, v16.4s, v17.4s
  sqdmlal2 v1.2d, v16.4s, v17.4s
  sqdmlal2 v2.2d, v16.4s, v17.4s
  sqdmlal2 v3.2d, v16.4s, v17.4s
  sqdmlal2 v4.2d, v16.4s, v17.4s
  sqdmlal2 v5.2d, v16.4s, v17.4s
  sqdmlal2 v6.2d, v16.4s, v17.4s
  sqdmlal2 v7.2d, v16.4s, v17.4s
  sqdmlal2 v8.2d, v16.4s, v17.4s
  sqdmlal2 v9.2d, v16.4s, v17.4s
  sqdmlal2 v10.2d, v16.4s, v17.4s
  sqdmlal2 v11.2d, v16.4s, v17.4s
  sqdmlal2 v12.2d, v16.4s, v17.4s
  sqdmlal2 v13.2d, v16.4s, v17.4s
  sqdmlal2 v14.2d, v16.4s, v17.4s
  sqdmlal2 v15.2d, v16.4s, v17.4s

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80057	160105	101	160004	100	160008	300	640044	160110	200	160014	200	480042	1	160000	100
160204	80035	160107	101	160006	100	160010	300	640208	160154	200	160063	200	480039	1	160000	100
160204	80035	160107	101	160006	100	160010	300	640044	160110	200	160013	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	480036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80113	160015	11	160004	10	160008	30	640044	160020	20	160014	20	480198	1	160000	10
160024	80049	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	480000	1	160000	10

SQDMLAL2 (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations