Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQDMLSL (scalar, D)

Test 1: uops

Code:

  sqdmlsl d0, s1, s2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000

Test 2: Latency 1->1

Code:

  sqdmlsl d0, s1, s2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042030000111000010
10024300331002121100002010000707689051002020100002030012111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024302341005321100322010132707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 3: Latency 1->2

Code:

  sqdmlsl d0, s0, s1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620030018110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1002430033100212110000201000070768905100202010006200300181101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010004200300001101000010

Test 4: Latency 1->3

Code:

  sqdmlsl d0, s1, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200301411101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqdmlsl d0, s8, s9
  movi v1.16b, 0
  sqdmlsl d1, s8, s9
  movi v2.16b, 0
  sqdmlsl d2, s8, s9
  movi v3.16b, 0
  sqdmlsl d3, s8, s9
  movi v4.16b, 0
  sqdmlsl d4, s8, s9
  movi v5.16b, 0
  sqdmlsl d5, s8, s9
  movi v6.16b, 0
  sqdmlsl d6, s8, s9
  movi v7.16b, 0
  sqdmlsl d7, s8, s9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044047380110101800091008001303000320056801132000800132002400391160000100
1602044012180110101800091008001303000320052801122000800122002400361160000100
1602044008680109101800081008001203000320052801122000800122002400361160000100
1602044008680109101800081008001203000320052801122000800122002400361160000100
1602044008680109101800081008001203000320052801122000800122002400361160000100
1602044008680109101800081008001203000320052801122000800122002400361160000100
1602044008680109101800081008001203000320052801122000800122002400361160000100
1602044008680109101800081008001203000320052801122000800122002400361160000100
1602044008680109101800081008001203000320052801122000800122002400361160000100
1602044008680109101800081008001203000320052801122000800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244386080020118000910800133032005680023208001320240000116000010
1600244128280011118000010800003032000080010208000020240000116000010
1600244045080011118000010800003032000080010208000020240000116000010
1600244041780011118000010800003032019680058208004820240000116000010
1600244043980011118000010800003032000080010208000020240000116000010
1600244041880011118000010800003032000080010208000020240000116000010
1600244038780011118000010800003032000080010208000020240000116000010
1600244041080011118000010800003032000080010208000020240000116000010
1600244038980011118000010800003032000080010208000020240000116000010
1600244037880011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  sqdmlsl d0, s16, s17
  sqdmlsl d1, s16, s17
  sqdmlsl d2, s16, s17
  sqdmlsl d3, s16, s17
  sqdmlsl d4, s16, s17
  sqdmlsl d5, s16, s17
  sqdmlsl d6, s16, s17
  sqdmlsl d7, s16, s17
  sqdmlsl d8, s16, s17
  sqdmlsl d9, s16, s17
  sqdmlsl d10, s16, s17
  sqdmlsl d11, s16, s17
  sqdmlsl d12, s16, s17
  sqdmlsl d13, s16, s17
  sqdmlsl d14, s16, s17
  sqdmlsl d15, s16, s17
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020480078160108101160007100160011300640044160110200160014200048003910160000100
16020480035160107101160006100160010300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640208160154200160061200048003610160000100
16020480035160107101160006100160010300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024801571600161116000510160009306400521600222016001520480042116000010
160024800411600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010
160024800441600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480192116000010
160024800351600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010
160024800351600111116000010160000306400001600102016000020480000116000010