Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQDMULH (by element, 2S)

Test 1: uops

Code:

  sqdmulh v0.2s, v0.2s, v1.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->2

Code:

  sqdmulh v0.2s, v0.2s, v1.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204300331010110110000010010000030007689051010020001000620020008110000100
10204300331010110110000010010000030007689051010020001000420020008110000100
10204300331010110110000010010000030007689051010020001000420020008110000100
10204300331010110110000010010000030007689051010020001000420020008110000100
10204300331010110110000010010000030007689051010020001000420220092210000100
10204300331010110110000010010000030007689051010020001000420020008110000100
10204300331010110110000010010000030007689051010020001000420020008110000100
10204300331010110110000010010000030007689051010020001000420020008110000100
10204300331010110110000010010000030007689051010020001000420020008110000100
10204300331010110110000010010000030007689051010020001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1002430033100212110000201000070768905100202010006200200001101000010
1002430033100212110000201000070768905100202010000200200001101000010
1002430033100212110000201000070768905100202010000200200001101000010
1002430033100212110000201000070768905100202010000200200001101000010
1002430033100212110000201000070768905100202010000200200001101000010
1002430033100212110000201000070768905100202010000200200001101000010
1002430033100212110000201000070768905100202010000200200001101000010
1002430033100212110000201000070768905100202010000200200001101000010
1002530066100272110006201003170768905100202010000200200001101000010
1002430085100292110008201003370768905100202010000200200001101000010

Test 3: Latency 1->3

Code:

  sqdmulh v0.2s, v1.2s, v0.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1002430033100212110000201000007007689051002020010006105843618422035948073299871014260066
1002430033100212110000201000007007689051002020010000200200001101000010
1002430033100212110000201000007007694511005320010040200200001101000010
1002430033100212110000201000007007689051002020010000200201621101000010
1002430033100212110000201000007007689051002020010000200200001101000010
1002430033100212110000201000006707699971008620010079200200001101000010
1002430033100212110000201000007007689051002020010000200200001101000010
1002430033100212110000201000007007689051002020010000200200001101000010
1002430033100212110000201000007007689051002020010000200200001101000010
1002430033100212110000201000006607694511005320010039200200761101000010

Test 4: throughput

Count: 8

Code:

  sqdmulh v0.2s, v8.2s, v9.s[1]
  sqdmulh v1.2s, v8.2s, v9.s[1]
  sqdmulh v2.2s, v8.2s, v9.s[1]
  sqdmulh v3.2s, v8.2s, v9.s[1]
  sqdmulh v4.2s, v8.2s, v9.s[1]
  sqdmulh v5.2s, v8.2s, v9.s[1]
  sqdmulh v6.2s, v8.2s, v9.s[1]
  sqdmulh v7.2s, v8.2s, v9.s[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
80204400558010810180007100800113003200448011020080014200160028180000100
80204400458010710180006100800103003200368010820080012200160024180000100
80204400358010510180004100800083003200368010820080012200160024180000100
80204400358010510180004100800083003200368010820080012200160024180000100
80204400358010510180004100800083003200368010820080012200160024180000100
80204400358010510180004100800083003200368010820080012200160024180000100
80204400358010510180004100800083003200368010820080012200160024180000100
80204400358010510180004100800083003200368010820080012200160024180000100
80204400358010510180004100800083003200368010820080012200160024180000100
80204400358010510180004100800083003200448011020080013200160028180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
800244015480029218000820800126532005280032208001720160000118000010
800244003580021218000020800006532000080020208000020160000118000010
800244003580021218000020800006532000080020208000020160000118000010
800244003580021218000020800006532000080020208000020160000118000010
800244003580021218000020800006532000080020208000020160000118000010
800244003580021218000020800006532000080020208000020160000118000010
800244003580021218000020800006532000080020208000020160000118000010
800244003580021218000020800006532000080020208000020160000118000010
800244003580021218000020800006532000080020208000020160000118000010
800244003580021218000020800006532000080020208000020160000118000010