Icestorm: SQRDMLAH (by element, 8H) measurements

Code:

  sqrdmlah v0.8h, v1.8h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  sqrdmlah v0.8h, v1.8h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30144	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30012	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  sqrdmlah v0.8h, v0.8h, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	30018	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10006	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  sqrdmlah v0.8h, v1.8h, v0.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30018	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrdmlah v0.8h, v8.8h, v9.h[1]
  movi v1.16b, 0
  sqrdmlah v1.8h, v8.8h, v9.h[1]
  movi v2.16b, 0
  sqrdmlah v2.8h, v8.8h, v9.h[1]
  movi v3.16b, 0
  sqrdmlah v3.8h, v8.8h, v9.h[1]
  movi v4.16b, 0
  sqrdmlah v4.8h, v8.8h, v9.h[1]
  movi v5.16b, 0
  sqrdmlah v5.8h, v8.8h, v9.h[1]
  movi v6.16b, 0
  sqrdmlah v6.8h, v8.8h, v9.h[1]
  movi v7.16b, 0
  sqrdmlah v7.8h, v8.8h, v9.h[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40450	80110	101	80009	100	80013	300	320200	80149	200	80049	200	240039	1	160000	100
160204	40110	80110	101	80009	100	80013	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	202	240147	2	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5054

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43715	80019	11	80008	10	80012	0	30	0	320056	80023	20	0	80013	20	240000	1	160000	10
160024	41157	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	41585	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40427	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40440	80011	11	80000	10	80000	0	30	0	320200	80059	20	0	80049	20	240000	1	160000	10
160024	40422	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40433	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240147	1	160000	10
160024	40779	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40412	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40437	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10

Test 6: throughput

Count: 12

Code:

  sqrdmlah v0.8h, v12.8h, v13.h[1]
  sqrdmlah v1.8h, v12.8h, v13.h[1]
  sqrdmlah v2.8h, v12.8h, v13.h[1]
  sqrdmlah v3.8h, v12.8h, v13.h[1]
  sqrdmlah v4.8h, v12.8h, v13.h[1]
  sqrdmlah v5.8h, v12.8h, v13.h[1]
  sqrdmlah v6.8h, v12.8h, v13.h[1]
  sqrdmlah v7.8h, v12.8h, v13.h[1]
  sqrdmlah v8.8h, v12.8h, v13.h[1]
  sqrdmlah v9.8h, v12.8h, v13.h[1]
  sqrdmlah v10.8h, v12.8h, v13.h[1]
  sqrdmlah v11.8h, v12.8h, v13.h[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
120204	60067	120108	101	120007	100	120011	300	480044	120110	200	120014	200	0	360036	1	0	120000	100
120204	60045	120107	101	120006	100	120010	300	480036	120108	200	120012	200	0	360036	1	0	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	0	360192	1	0	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	0	360039	1	0	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	0	360036	1	0	120000	100
120204	60035	120107	101	120006	100	120010	300	480036	120108	200	120012	200	0	360036	1	0	120000	100
120204	60045	120107	101	120006	100	120010	300	480044	120110	200	120014	200	0	360036	1	0	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	0	360036	1	0	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	0	360036	1	0	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	0	360036	1	0	120000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
120024	60137	120016	11	120005	10	120009	30	480052	120022	20	120015	20	360045	1	120000	10
120024	60401	120213	11	120202	10	120206	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480208	120064	20	120061	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480044	120020	20	120014	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10

SQRDMLAH (by element, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations