Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQRDMLAH (scalar, S)

Test 1: uops

Code:

  sqrdmlah s0, s1, s2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000

Test 2: Latency 1->1

Code:

  sqrdmlah s0, s1, s2
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042030000111000010
10024300331002121100002010000707689051002020100002030120111000010
10024300331002121100002010000707689051002020100002030000111000010
10024301441002921100082010033707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 3: Latency 1->2

Code:

  sqrdmlah s0, s0, s1
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000620030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100
10204300331010110110000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030132111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 4: Latency 1->3

Code:

  sqrdmlah s0, s1, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620030018110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010
1002430033100212110000201000070768905100202010000200300001101000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrdmlah s0, s8, s9
  movi v1.16b, 0
  sqrdmlah s1, s8, s9
  movi v2.16b, 0
  sqrdmlah s2, s8, s9
  movi v3.16b, 0
  sqrdmlah s3, s8, s9
  movi v4.16b, 0
  sqrdmlah s4, s8, s9
  movi v5.16b, 0
  sqrdmlah s5, s8, s9
  movi v6.16b, 0
  sqrdmlah s6, s8, s9
  movi v7.16b, 0
  sqrdmlah s7, s8, s9
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044049980109101800081008001230032005680113200800132002400391160000100
1602044011080110101800091008001330032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005680113200800132002400391160000100
1602044008680109101800081008001230032005280112200800122002400391160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244384780019118000810800123032000080010208000020240000116000010
1600244127080011118000010800003032000080010208000020240000116000010
1600244039780011118000010800003032000080010208000020240000116000010
1600244038680011118000010800003032000080010208000020240000116000010
1600244042780011118000010800003032000080010208000020240000116000010
1600244041580011118000010800003032000080010208000020240000116000010
1600244040480011118000010800003032000080010208000020240000116000010
1600244040480011118000010800003032000080010208000020240000116000010
1600244039780011118000010800003032000080010208000020240000116000010
1600244041380011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  sqrdmlah s0, s16, s17
  sqrdmlah s1, s16, s17
  sqrdmlah s2, s16, s17
  sqrdmlah s3, s16, s17
  sqrdmlah s4, s16, s17
  sqrdmlah s5, s16, s17
  sqrdmlah s6, s16, s17
  sqrdmlah s7, s16, s17
  sqrdmlah s8, s16, s17
  sqrdmlah s9, s16, s17
  sqrdmlah s10, s16, s17
  sqrdmlah s11, s16, s17
  sqrdmlah s12, s16, s17
  sqrdmlah s13, s16, s17
  sqrdmlah s14, s16, s17
  sqrdmlah s15, s16, s17
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020480096160105101160004100160008300640044160110200160014200048003910160000100
16020480045160107101160006100160010300640044160110200160014200048019210160000100
16020480045160107101160006100160010300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100
16020480035160107101160006100160010300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100
16020480035160105101160004100160008300640036160108200160012200048003610160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024801981600151116000410160008030064004416002020016001420480000116000010
160024800411600111116000010160000030064000016001020016000020480000116000010
160024800351600111116000010160000030064000016001020016000020480000116000010
160024800351600111116000010160000030064000016001020016000020480000116000010
160024800551600111116000010160000030064000016001020016000020480000116000010
160024800351600111116000010160000030064000016001020016000020480000116000010
160024800351600111116000010160000030064000016001020016000020480000116000010
160024800351600111116000010160000030064000016001020016000020480000116000010
160024800351600111116000010160000030064000016001020016000020480000116000010
160024800351600111116000010160000030064000016001020016000020480000116000010