Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQRDMLAH (vector, 4H)

Test 1: uops

Code:

  sqrdmlah v0.4h, v1.4h, v2.4h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000
1004303310011100010007590510001000300011000

Test 2: Latency 1->1

Code:

  sqrdmlah v0.4h, v1.4h, v2.4h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030144111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010
10024300331002121100002010000070076890510020200100002030000111000010

Test 3: Latency 1->2

Code:

  sqrdmlah v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620030018110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030141110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100062030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 4: Latency 1->3

Code:

  sqrdmlah v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620030018110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100
1020430033101011011000010010000300768905101002001000420030012110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100062030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000687692471005120100482030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010
10024300331002121100002010000657689051002020100002030000111000010
10024300331002121100002010000707689051002020100002030000111000010

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrdmlah v0.4h, v8.4h, v9.4h
  movi v1.16b, 0
  sqrdmlah v1.4h, v8.4h, v9.4h
  movi v2.16b, 0
  sqrdmlah v2.4h, v8.4h, v9.4h
  movi v3.16b, 0
  sqrdmlah v3.4h, v8.4h, v9.4h
  movi v4.16b, 0
  sqrdmlah v4.4h, v8.4h, v9.4h
  movi v5.16b, 0
  sqrdmlah v5.4h, v8.4h, v9.4h
  movi v6.16b, 0
  sqrdmlah v6.4h, v8.4h, v9.4h
  movi v7.16b, 0
  sqrdmlah v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044047580110101800091008001330032005680113200800132002400391160000100
1602044009980110101800091008001330032005280112200800122002400361160000100
1602044009880110101800091008001330032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005680113200800132002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100
1602044008680109101800081008001230032005280112200800122002400361160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244369480019118000810800123032005680023208001320240000116000010
1600244120880011118000010800003032000080010208000020240000116000010
1600244039380011118000010800003032000080010208000020240000116000010
1600244038680011118000010800003032005680023208001320240000116000010
1600244046680011118000010800003032000080010208000020240000116000010
1600244041780011118000010800003032000080010208000020240000116000010
1600244040780011118000010800003032000080010208000020240000116000010
1600244041680011118000010800003032000080010208000020240000116000010
1600244041680011118000010800003032000080010208000020240000116000010
1600244039680011118000010800003032000080010208000020240000116000010

Test 6: throughput

Count: 16

Code:

  sqrdmlah v0.4h, v16.4h, v17.4h
  sqrdmlah v1.4h, v16.4h, v17.4h
  sqrdmlah v2.4h, v16.4h, v17.4h
  sqrdmlah v3.4h, v16.4h, v17.4h
  sqrdmlah v4.4h, v16.4h, v17.4h
  sqrdmlah v5.4h, v16.4h, v17.4h
  sqrdmlah v6.4h, v16.4h, v17.4h
  sqrdmlah v7.4h, v16.4h, v17.4h
  sqrdmlah v8.4h, v16.4h, v17.4h
  sqrdmlah v9.4h, v16.4h, v17.4h
  sqrdmlah v10.4h, v16.4h, v17.4h
  sqrdmlah v11.4h, v16.4h, v17.4h
  sqrdmlah v12.4h, v16.4h, v17.4h
  sqrdmlah v13.4h, v16.4h, v17.4h
  sqrdmlah v14.4h, v16.4h, v17.4h
  sqrdmlah v15.4h, v16.4h, v17.4h
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800721601051011600041001600083006400441601102001600142024835792160000100
160204844971630731011629721001629763306510961628832101627772004883101160000100
160204843491629491051628441041628523126516521630162041629162044885922160000100
160204800901601571011600561001600603006400361601082001600122004800361160000100
160204831921621801011620791001620833036521241631312021630342044887783160000100
160204846681631611031630581021630623216518681630732081629702064888144160000100
160204831751621761041620721031620763006400361601082001600122004800361160000100
160204802681602561031601531021601573006473001619242001618282044886223160000100
160204845351630471091629381081629463066544121637042021636062084972504160000100
160204838561626301041625261031625303006402401601592001600632044988372160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024803201600151116000410160008306400441600202016001420480000116000010
160024800681600111116000010160000306400001600102016000020480000116000010
160024800391600111116000010160000306400001600102016000020480000116000010
160024800391600111116000010160000306400001600102016000020480000116000010
160024800391600111116000010160000306400001600102016000020480000116000010
160024800391600111116000010160000306400001600102016000020480000116000010
160024800391600111116000010160000306400001600102016000020480585116000010
160024800391600111116000010160000306400001600102016000020480000116000010
160024800391600111116000010160000306400001600102016000020480000116000010
160024800391600111116000010160000306400001600102016000020480000116000010