Icestorm: SQRDMLSH (by element, H) measurements

Code:

  sqrdmlsh h0, h1, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  sqrdmlsh h0, h1, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0802

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30851	10235	107	10128	106	10528	335	778172	10671	210	10681	208	31902	4	10000	100
10204	30906	10249	113	10136	112	10561	361	776234	10573	218	10552	212	32040	5	10000	100
10204	30907	10249	113	10136	112	10561	314	777626	10632	204	10641	208	31476	5	10000	100
10204	30951	10247	103	10144	102	10594	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	307	769451	10135	202	10046	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 3: Latency 1->2

Code:

  sqrdmlsh h0, h0, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	30018	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 4: Latency 1->3

Code:

  sqrdmlsh h0, h1, v0.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	0	30018	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	0	30012	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrdmlsh h0, h8, v9.h[1]
  movi v1.16b, 0
  sqrdmlsh h1, h8, v9.h[1]
  movi v2.16b, 0
  sqrdmlsh h2, h8, v9.h[1]
  movi v3.16b, 0
  sqrdmlsh h3, h8, v9.h[1]
  movi v4.16b, 0
  sqrdmlsh h4, h8, v9.h[1]
  movi v5.16b, 0
  sqrdmlsh h5, h8, v9.h[1]
  movi v6.16b, 0
  sqrdmlsh h6, h8, v9.h[1]
  movi v7.16b, 0
  sqrdmlsh h7, h8, v9.h[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40536	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240039	1	160000	100
160204	40110	80110	101	80009	100	80013	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5051

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43820	80020	11	80009	10	80013	30	320000	80010	20	80000	20	240000	1	160000	10
160024	41357	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40480	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40409	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40406	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40368	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40399	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40388	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40411	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10
160024	40392	80011	11	80000	10	80000	30	320000	80010	20	80000	20	240000	1	160000	10

Test 6: throughput

Count: 12

Code:

  sqrdmlsh h0, h12, v13.h[1]
  sqrdmlsh h1, h12, v13.h[1]
  sqrdmlsh h2, h12, v13.h[1]
  sqrdmlsh h3, h12, v13.h[1]
  sqrdmlsh h4, h12, v13.h[1]
  sqrdmlsh h5, h12, v13.h[1]
  sqrdmlsh h6, h12, v13.h[1]
  sqrdmlsh h7, h12, v13.h[1]
  sqrdmlsh h8, h12, v13.h[1]
  sqrdmlsh h9, h12, v13.h[1]
  sqrdmlsh h10, h12, v13.h[1]
  sqrdmlsh h11, h12, v13.h[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
120204	60099	120105	101	120004	100	120008	300	480044	120110	200	120014	200	360039	1	120000	100
120204	60035	120107	101	120006	100	120010	300	480036	120108	200	120012	200	360198	1	120000	100
120204	60045	120107	101	120006	100	120010	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120204	60035	120105	101	120004	100	120008	300	480036	120108	200	120012	200	360036	1	120000	100
120205	60070	120141	101	120040	100	120052	300	480040	120109	200	120013	200	360042	1	120000	100
120204	60045	120107	101	120006	100	120010	300	480036	120108	200	120012	200	360036	1	120000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5003

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
120024	60197	120016	11	120005	10	120009	30	480044	120020	20	120014	20	360039	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480200	120062	20	120059	20	360186	1	120000	10
120024	60073	120019	11	120008	10	120012	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10
120024	60035	120011	11	120000	10	120000	30	480000	120010	20	120000	20	360000	1	120000	10

SQRDMLSH (by element, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations