Icestorm: SQRDMLSH (vector, 8H) measurements

Code:

  sqrdmlsh v0.8h, v1.8h, v2.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	3000	1	1000

Test 2: Latency 1->1

Code:

  sqrdmlsh v0.8h, v1.8h, v2.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	769247	10051	20	10044	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	30000	11	0	10000	10

Test 3: Latency 1->2

Code:

  sqrdmlsh v0.8h, v0.8h, v1.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	30012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10006	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10502	33694	10603	374	10006	223	372	10031	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30252	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	30012	11	10000	10

Test 4: Latency 1->3

Code:

  sqrdmlsh v0.8h, v1.8h, v0.8h

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10006	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10006	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	0	30012	1	0	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	0	30012	1	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	30000	11	10000	10

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrdmlsh v0.8h, v8.8h, v9.8h
  movi v1.16b, 0
  sqrdmlsh v1.8h, v8.8h, v9.8h
  movi v2.16b, 0
  sqrdmlsh v2.8h, v8.8h, v9.8h
  movi v3.16b, 0
  sqrdmlsh v3.8h, v8.8h, v9.8h
  movi v4.16b, 0
  sqrdmlsh v4.8h, v8.8h, v9.8h
  movi v5.16b, 0
  sqrdmlsh v5.8h, v8.8h, v9.8h
  movi v6.16b, 0
  sqrdmlsh v6.8h, v8.8h, v9.8h
  movi v7.16b, 0
  sqrdmlsh v7.8h, v8.8h, v9.8h

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40481	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240039	1	160000	100
160204	40105	80109	101	80008	100	80012	300	320056	80113	200	80013	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	240036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43938	80019	11	80008	10	80012	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	41260	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240150	1	160000	10
160024	40423	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160025	40720	80048	11	80037	10	80037	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40415	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	44494	80020	11	80009	10	80013	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40446	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40385	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40391	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10
160024	40372	80011	11	80000	10	80000	0	30	0	320000	80010	20	0	80000	20	240000	1	160000	10

Test 6: throughput

Count: 16

Code:

  sqrdmlsh v0.8h, v16.8h, v17.8h
  sqrdmlsh v1.8h, v16.8h, v17.8h
  sqrdmlsh v2.8h, v16.8h, v17.8h
  sqrdmlsh v3.8h, v16.8h, v17.8h
  sqrdmlsh v4.8h, v16.8h, v17.8h
  sqrdmlsh v5.8h, v16.8h, v17.8h
  sqrdmlsh v6.8h, v16.8h, v17.8h
  sqrdmlsh v7.8h, v16.8h, v17.8h
  sqrdmlsh v8.8h, v16.8h, v17.8h
  sqrdmlsh v9.8h, v16.8h, v17.8h
  sqrdmlsh v10.8h, v16.8h, v17.8h
  sqrdmlsh v11.8h, v16.8h, v17.8h
  sqrdmlsh v12.8h, v16.8h, v17.8h
  sqrdmlsh v13.8h, v16.8h, v17.8h
  sqrdmlsh v14.8h, v16.8h, v17.8h
  sqrdmlsh v15.8h, v16.8h, v17.8h

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80058	160105	101	160004	100	160008	0	300	0	640044	160110	200	0	160014	200	480042	1	160000	100
160204	80045	160107	101	160006	100	160010	0	300	0	640044	160110	200	0	160014	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640044	160110	200	0	160013	200	480039	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	480036	1	160000	100
160204	80035	160105	101	160004	100	160008	0	300	0	640036	160108	200	0	160012	200	480036	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	80161	160018	11	160007	0	10	160011	0	30	0	640204	160063	20	0	160062	20	0	480189	1	0	160000	10
160024	80350	160018	11	160007	0	10	160011	0	30	0	640044	160020	20	0	160013	20	0	480039	1	0	160000	10
160024	80047	160017	11	160006	0	10	160010	0	30	0	640044	160020	20	0	160013	20	0	480039	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	0	480000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	0	480042	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	0	480000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	0	480180	1	0	160000	10
160024	80271	160110	11	160099	0	10	160099	0	30	0	640588	160157	20	0	160147	20	0	480000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	0	480000	1	0	160000	10
160024	80035	160011	11	160000	0	10	160000	0	30	0	640000	160010	20	0	160000	20	0	480000	1	0	160000	10

SQRDMLSH (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations