Icestorm: SQRDMULH (scalar, H) measurements

Code:

  sqrdmulh h0, h0, h1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->2

Code:

  sqrdmulh h0, h0, h1

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	30291	10147	107	10040	0	106	10165	300	768905	10100	200	10006	200	0	20008	1	0	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	0	20008	1	0	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	0	20008	1	0	10000	100
10204	30033	10101	101	10000	0	100	10000	314	771074	10236	204	10163	2296	1560	20086	832	669	10003	1139
10204	30236	10135	103	10032	0	102	10132	300	768905	10100	200	10006	200	0	20168	1	0	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	202	0	20172	2	0	10000	100
10204	30033	10101	101	10000	0	100	10000	300	769436	10133	200	10045	200	0	20008	1	0	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10006	200	0	20012	1	0	10000	100
10204	30033	10101	101	10000	0	100	10000	300	769451	10133	202	10046	206	0	20400	4	0	10000	100
10204	30544	10188	108	10080	0	107	10330	328	773258	10372	208	10320	208	0	20714	5	0	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10006	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->3

Code:

  sqrdmulh h0, h1, h0

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10006	200	20012	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20088	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10205	30066	10107	101	10006	0	100	10031	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	0	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10006	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	20000	11	0	10000	10
10025	30066	10027	21	10006	20	10031	70	768905	10020	20	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	20000	11	0	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	0	20086	11	0	10000	10

Test 4: throughput

Count: 8

Code:

  sqrdmulh h0, h8, h9
  sqrdmulh h1, h8, h9
  sqrdmulh h2, h8, h9
  sqrdmulh h3, h8, h9
  sqrdmulh h4, h8, h9
  sqrdmulh h5, h8, h9
  sqrdmulh h6, h8, h9
  sqrdmulh h7, h8, h9

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40061	80105	101	80004	100	80008	300	320044	80110	200	80014	200	160028	1	80000	100
80204	40045	80107	101	80006	100	80010	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40035	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40035	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40035	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40035	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40035	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40035	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40035	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100
80204	40035	80105	101	80004	100	80008	300	320036	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40219	80028	21	80007	20	80011	65	320052	80032	20	80017	20	160000	11	80000	10
80024	40037	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	64	320380	80120	20	80114	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	69	320000	80020	20	80000	20	160000	11	80000	10
80025	40073	80066	21	80045	20	80057	69	320000	80020	20	80000	20	160000	11	80000	10
80024	40035	80021	21	80000	20	80000	65	320000	80020	20	80000	20	160000	11	80000	10

SQRDMULH (scalar, H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations