Icestorm: SQRSHRUN2 (2D) measurements

Code:

  sqrshrun2 v0.4s, v1.2d, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  sqrshrun2 v0.4s, v1.2d, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10006	200	20012	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	0	300	0	768905	10100	200	0	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	66	769247	10051	20	10046	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20096	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  sqrshrun2 v0.4s, v0.2d, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30085	10111	103	10008	102	10033	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20320	11	10000	10
10024	30033	10021	21	10000	20	10000	69	769451	10053	20	10041	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrshrun2 v0.4s, v8.2d, #3
  movi v1.16b, 0
  sqrshrun2 v1.4s, v8.2d, #3
  movi v2.16b, 0
  sqrshrun2 v2.4s, v8.2d, #3
  movi v3.16b, 0
  sqrshrun2 v3.4s, v8.2d, #3
  movi v4.16b, 0
  sqrshrun2 v4.4s, v8.2d, #3
  movi v5.16b, 0
  sqrshrun2 v5.4s, v8.2d, #3
  movi v6.16b, 0
  sqrshrun2 v6.4s, v8.2d, #3
  movi v7.16b, 0
  sqrshrun2 v7.4s, v8.2d, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160206	40667	80181	101	80080	0	100	80084	300	320052	80112	200	80012	200	160026	1	160000	100
160204	40108	80110	101	80009	0	100	80013	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320196	80148	200	80048	200	160024	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5056

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43796	80019	11	80008	10	80012	30	320052	80022	20	80012	20	160000	1	160000	10
160024	41237	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40480	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40411	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40409	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40371	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160094	1	160000	10
160024	40476	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40395	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	44271	80019	11	80008	10	80012	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40466	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  sqrshrun2 v0.4s, v16.2d, #3
  sqrshrun2 v1.4s, v16.2d, #3
  sqrshrun2 v2.4s, v16.2d, #3
  sqrshrun2 v3.4s, v16.2d, #3
  sqrshrun2 v4.4s, v16.2d, #3
  sqrshrun2 v5.4s, v16.2d, #3
  sqrshrun2 v6.4s, v16.2d, #3
  sqrshrun2 v7.4s, v16.2d, #3
  sqrshrun2 v8.4s, v16.2d, #3
  sqrshrun2 v9.4s, v16.2d, #3
  sqrshrun2 v10.4s, v16.2d, #3
  sqrshrun2 v11.4s, v16.2d, #3
  sqrshrun2 v12.4s, v16.2d, #3
  sqrshrun2 v13.4s, v16.2d, #3
  sqrshrun2 v14.4s, v16.2d, #3
  sqrshrun2 v15.4s, v16.2d, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80072	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160107	101	160006	100	160010	300	640036	160108	200	160012	200	320128	1	160000	100
160204	80035	160107	101	160006	100	160010	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320128	1	160000	100
160204	80035	160107	101	160006	100	160010	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160107	101	160006	100	160010	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320128	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	80138	160017	11	160006	10	160010	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80051	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	30	640200	160062	20	160060	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80058	160017	11	160006	10	160010	30	640036	160018	20	160012	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320028	1	0	160000	10
160024	80045	160015	11	160004	10	160008	30	640000	160010	20	160000	20	0	320000	1	0	160000	10

SQRSHRUN2 (2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations