Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQRSHRUN2 (2D)

Test 1: uops

Code:

  sqrshrun2 v0.4s, v1.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->1

Code:

  sqrshrun2 v0.4s, v1.2d, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000030007689051010020001000620020012110000100
1020430033101011011000010010000030007689051010020001000420020008110000100
1020430033101011011000010010000030007689051010020001000420020008110000100
1020430033101011011000010010000030007689051010020001000420020008110000100
1020430033101011011000010010000030007689051010020001000420020008110000100
1020430033101011011000010010000030007689051010020001000420020008110000100
1020430033101011011000010010000030007689051010020001000420020008110000100
1020430033101011011000010010000030007689051010020001000420020008110000100
1020430033101011011000010010000030007689051010020001000420020008110000100
1020430033101011011000010010000030007689051010020001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000667692471005120100462020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020096111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010

Test 3: Latency 1->2

Code:

  sqrshrun2 v0.4s, v0.2d, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430085101111031000810210033300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020320111000010
10024300331002121100002010000697694511005320100412020000111000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqrshrun2 v0.4s, v8.2d, #3
  movi v1.16b, 0
  sqrshrun2 v1.4s, v8.2d, #3
  movi v2.16b, 0
  sqrshrun2 v2.4s, v8.2d, #3
  movi v3.16b, 0
  sqrshrun2 v3.4s, v8.2d, #3
  movi v4.16b, 0
  sqrshrun2 v4.4s, v8.2d, #3
  movi v5.16b, 0
  sqrshrun2 v5.4s, v8.2d, #3
  movi v6.16b, 0
  sqrshrun2 v6.4s, v8.2d, #3
  movi v7.16b, 0
  sqrshrun2 v7.4s, v8.2d, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
16020640667801811018008001008008430032005280112200800122001600261160000100
16020440108801101018000901008001330032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032019680148200800482001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5056

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244379680019118000810800123032005280022208001220160000116000010
1600244123780011118000010800003032000080010208000020160000116000010
1600244048080011118000010800003032000080010208000020160000116000010
1600244041180011118000010800003032000080010208000020160000116000010
1600244040980011118000010800003032000080010208000020160000116000010
1600244037180011118000010800003032000080010208000020160094116000010
1600244047680011118000010800003032000080010208000020160000116000010
1600244039580011118000010800003032000080010208000020160000116000010
1600244427180019118000810800123032000080010208000020160000116000010
1600244046680011118000010800003032000080010208000020160000116000010

Test 5: throughput

Count: 16

Code:

  sqrshrun2 v0.4s, v16.2d, #3
  sqrshrun2 v1.4s, v16.2d, #3
  sqrshrun2 v2.4s, v16.2d, #3
  sqrshrun2 v3.4s, v16.2d, #3
  sqrshrun2 v4.4s, v16.2d, #3
  sqrshrun2 v5.4s, v16.2d, #3
  sqrshrun2 v6.4s, v16.2d, #3
  sqrshrun2 v7.4s, v16.2d, #3
  sqrshrun2 v8.4s, v16.2d, #3
  sqrshrun2 v9.4s, v16.2d, #3
  sqrshrun2 v10.4s, v16.2d, #3
  sqrshrun2 v11.4s, v16.2d, #3
  sqrshrun2 v12.4s, v16.2d, #3
  sqrshrun2 v13.4s, v16.2d, #3
  sqrshrun2 v14.4s, v16.2d, #3
  sqrshrun2 v15.4s, v16.2d, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800721601051011600041001600083006400361601082001600122003200241160000100
160204800351601071011600061001600103006400361601082001600122003201281160000100
160204800351601071011600061001600103006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003201281160000100
160204800351601071011600061001600103006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601071011600061001600103006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003201281160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002480138160017111600061016001030640000160010201600002003200001016000010
16002480051160011111600001016000030640000160010201600002003200001016000010
16002480035160011111600001016000030640200160062201600602003200001016000010
16002480035160011111600001016000030640000160010201600002003200001016000010
16002480035160011111600001016000030640000160010201600002003200001016000010
16002480035160011111600001016000030640000160010201600002003200001016000010
16002480035160011111600001016000030640000160010201600002003200001016000010
16002480058160017111600061016001030640036160018201600122003200001016000010
16002480035160011111600001016000030640000160010201600002003200281016000010
16002480045160015111600041016000830640000160010201600002003200001016000010