Icestorm: SQSHLU (vector, 2S) measurements

Code:

  sqshlu v0.2s, v0.2s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000
1004	2033	1001	1	1000	1000	50248	1000	1000	1000	1	1000

Test 2: Latency 1->2

Code:

  sqshlu v0.2s, v0.2s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10006	202	10048	2	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10006	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10006	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10006	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	307	509580	10136	202	10046	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20135	10047	23	10024	22	10072	66	510312	10092	20	10085	20	10132	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	10000	11	10000	10
10024	20135	10045	21	10024	20	10072	70	509780	10056	20	10040	20	10125	11	10000	10
10024	20137	10045	21	10024	20	10072	69	510844	10128	20	10124	20	10123	11	10000	10
10024	20136	10045	21	10024	20	10072	75	510844	10130	22	10124	20	10082	11	10000	10
10024	20137	10045	21	10024	20	10072	67	510296	10092	20	10081	20	10082	11	10000	10
10024	20084	10033	21	10012	20	10036	75	510844	10130	22	10126	20	10082	11	10000	10
10024	20135	10045	21	10024	20	10072	66	510312	10092	20	10083	20	10126	11	10000	10
10024	20189	10057	21	10036	20	10108	68	510312	10092	20	10085	22	10123	12	10000	10
10024	20188	10057	21	10036	20	10108	72	510844	10130	22	10122	20	10124	11	10000	10

Test 3: throughput

Count: 8

Code:

  sqshlu v0.2s, v8.2s, #3
  sqshlu v1.2s, v8.2s, #3
  sqshlu v2.2s, v8.2s, #3
  sqshlu v3.2s, v8.2s, #3
  sqshlu v4.2s, v8.2s, #3
  sqshlu v5.2s, v8.2s, #3
  sqshlu v6.2s, v8.2s, #3
  sqshlu v7.2s, v8.2s, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80204	40057	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80107	101	80006	100	80010	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80204	40034	80105	101	80004	100	80008	300	320036	80108	200	80012	200	80012	1	80000	100
80205	40069	80143	101	80042	100	80054	300	320044	80110	200	80014	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
80024	40120	80029	21	80008	20	80012	0	70	0	320000	80020	20	0	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	80000	11	80000	10
80025	40069	80063	21	80042	20	80054	0	70	0	320000	80020	20	0	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	80000	11	80000	10
80024	40034	80021	21	80000	20	80000	0	70	0	320000	80020	20	0	80000	20	80064	11	80000	10

SQSHLU (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations