Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQSHRUN2 (4S)

Test 1: uops

Code:

  sqshrun2 v0.8h, v1.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->1

Code:

  sqshrun2 v0.8h, v1.4s, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
102043003310101101100001001000030076890510100200100062000200121010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102053006610107101100061001003130076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200081010000100
102043003310101101100001001000030076890510100200100042000200101010000100
102043003310101101100001001000030076890510100200100042000200121010000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000070076890510020200100062020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076890510020200100002020000111000010
10024300331002121100002010000070076924710051200100442020000111000010
10024300331002121100002010000070076890510020200100002020000111000010

Test 3: Latency 1->2

Code:

  sqshrun2 v0.8h, v0.4s, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042020000111000010
10024300331002121100002010000707692471005120100442020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqshrun2 v0.8h, v8.4s, #3
  movi v1.16b, 0
  sqshrun2 v1.8h, v8.4s, #3
  movi v2.16b, 0
  sqshrun2 v2.8h, v8.4s, #3
  movi v3.16b, 0
  sqshrun2 v3.8h, v8.4s, #3
  movi v4.16b, 0
  sqshrun2 v4.8h, v8.4s, #3
  movi v5.16b, 0
  sqshrun2 v5.8h, v8.4s, #3
  movi v6.16b, 0
  sqshrun2 v6.8h, v8.4s, #3
  movi v7.16b, 0
  sqshrun2 v7.8h, v8.4s, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044047680109101800081008001230032005280112200800122001600261160000100
1602044011080110101800091008001330032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005680113200800132001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032020480150200800502001600241160000100
1602044010180110101800091008001330032005280112200800122001600241160000100
1602044008680109101800081008001230032005680113200800132001600241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244385480019118000810800120300320052800222008001220160000116000010
1600244128280011118000010800000300320000800102008000020160000116000010
1600244043680011118000010800000300320000800102008000020160000116000010
1600244043280011118000010800000300320000800102008000020160000116000010
1600244043680011118000010800000300320000800102008000020160000116000010
1600244042780011118000010800000300320000800102008000020160000116000010
1600244038880011118000010800000300320000800102008000020160000116000010
1600244042780011118000010800000300320200800592008004920160000116000010
1600244039080011118000010800000300320000800102008000020160000116000010
1600244043480011118000010800000300320000800102008000020160000116000010

Test 5: throughput

Count: 16

Code:

  sqshrun2 v0.8h, v16.4s, #3
  sqshrun2 v1.8h, v16.4s, #3
  sqshrun2 v2.8h, v16.4s, #3
  sqshrun2 v3.8h, v16.4s, #3
  sqshrun2 v4.8h, v16.4s, #3
  sqshrun2 v5.8h, v16.4s, #3
  sqshrun2 v6.8h, v16.4s, #3
  sqshrun2 v7.8h, v16.4s, #3
  sqshrun2 v8.8h, v16.4s, #3
  sqshrun2 v9.8h, v16.4s, #3
  sqshrun2 v10.8h, v16.4s, #3
  sqshrun2 v11.8h, v16.4s, #3
  sqshrun2 v12.8h, v16.4s, #3
  sqshrun2 v13.8h, v16.4s, #3
  sqshrun2 v14.8h, v16.4s, #3
  sqshrun2 v15.8h, v16.4s, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800761601071011600061001600100300064003616010820001600122003201221160000100
160204800541601051011600041001600080300064003616010820001600122003201221160000100
160204800351601071011600061001600100300064003616010820001600122003200241160000100
160204800351601051011600041001600080300064003616010820001600122003200241160000100
160204800351601051011600041001600080300064003616010820001600122003200241160000100
160204800351601051011600041001600080300064020816015420001600642003200241160000100
160204800351601051011600041001600080300064003616010820001600122003200241160000100
160204800351601051011600041001600080300064003616010820001600122003200241160000100
160204800351601051011600041001600080300064003616010820001600122003200241160000100
160204800351601051011600041001600080300064003616010820001600122003200241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160025801731600531116004210160054030064003616001820016001220320000116000010
160024800351600111116000010160000030064000016001020016000020320000116000010
160024800351600111116000010160000030064000016001020016000020320000116000010
160024800481600111116000010160000030064000016001020016000020320000116000010
160024800351600111116000010160000030064000016001020016000020320000116000010
160024800351600111116000010160000030064000016001020016000020320000116000010
160024800351600111116000010160000030064000016001020016000020320000116000010
160024800351600111116000010160000030064000016001020016000020320000116000010
160024800351600111116000010160000030064000016001020016000020320000116000010
160024800351600111116000010160000030064000016001020016000020320000116000010