Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SQXTUN2 (2D)

Test 1: uops

Code:

  sqxtun2 v0.4s, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->1

Code:

  sqxtun2 v0.4s, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620020012110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042020012111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010

Test 3: Latency 1->2

Code:

  sqxtun2 v0.4s, v0.2d
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420220086210000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1002430033100212110000201000070768905100202010000200200881101000010
1002430033100212110000201000070768905100202010000200200001101000010
1002430033100212110000201000070768905100202010000200200001101000010
1002430033100212110000201000070768905100202010000200200001101000010
1002430033100212110000201000070768905100202010000200200001101000010
1002430033100212110000201000070768905100202010000200200001101000010
1002430033100212110000201000070768905100202010004200200001101000010
1002430033100212110000201000070768905100202010000200200001101000010
1002430033100212110000201000070768905100202010000200200001101000010
1002430033100212110000201000070768905100202010000200200081101000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sqxtun2 v0.4s, v8.2d
  movi v1.16b, 0
  sqxtun2 v1.4s, v8.2d
  movi v2.16b, 0
  sqxtun2 v2.4s, v8.2d
  movi v3.16b, 0
  sqxtun2 v3.4s, v8.2d
  movi v4.16b, 0
  sqxtun2 v4.4s, v8.2d
  movi v5.16b, 0
  sqxtun2 v5.4s, v8.2d
  movi v6.16b, 0
  sqxtun2 v6.4s, v8.2d
  movi v7.16b, 0
  sqxtun2 v7.4s, v8.2d
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044046780109101800081008001203000320196801482000800482001600241160000100
1602044010580110101800091008001303000320056801132000800132001600261160000100
1602044008680109101800081008001203000320052801122000800122001600241160000100
1602044008680109101800081008001203000320052801122000800122001600241160000100
1602044008680109101800081008001203000320052801122000800122001600241160000100
1602044008680109101800081008001203000320052801122000800122001600261160000100
1602044009680110101800091008001303000320052801122000800122001600241160000100
1602044008680109101800081008001203000320052801122000800122001600241160000100
1602044008680109101800081008001203000320052801122000800122001600241160000100
1602044008680109101800081008001203030320200801502020800492001600241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
16002443689800201180009010800130300320056800232008001320160000116000010
16002441219800111180000010800000300320000800102008000020160000116000010
16002440419800111180000010800000300320000800102008000020160000116000010
16002440430800111180000010800000300320000800102008000020160000116000010
16002440446800111180000010800000300320000800102008000020160000116000010
16002440437800111180000010800000300320000800102008000020160000116000010
16002440399800111180000010800000300320000800102008000020160000116000010
16002440413800111180000010800000300320000800102008000020160000116000010
16002440427800111180000010800000300320000800102008000020160000116000010
16002440467800111180000010800000300320000800102008000020160000116000010

Test 5: throughput

Count: 16

Code:

  sqxtun2 v0.4s, v16.2d
  sqxtun2 v1.4s, v16.2d
  sqxtun2 v2.4s, v16.2d
  sqxtun2 v3.4s, v16.2d
  sqxtun2 v4.4s, v16.2d
  sqxtun2 v5.4s, v16.2d
  sqxtun2 v6.4s, v16.2d
  sqxtun2 v7.4s, v16.2d
  sqxtun2 v8.4s, v16.2d
  sqxtun2 v9.4s, v16.2d
  sqxtun2 v10.4s, v16.2d
  sqxtun2 v11.4s, v16.2d
  sqxtun2 v12.4s, v16.2d
  sqxtun2 v13.4s, v16.2d
  sqxtun2 v14.4s, v16.2d
  sqxtun2 v15.4s, v16.2d
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204801261601051011600041001600083006400361601082001600122003200281160000100
160204800351601071011600061001600103006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003201281160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024801211600151116000410160008306400441600202016001420320000116000010
160024800701600111116000010160000306400001600102016000020320100116000010
160024802581601581116014710160147306400001600102016000020320000116000010
160025800701600471116003610160044306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160024800351600111116000010160000306400001600102016000020320000116000010
160024800371600111116000010160000306400001600102016000020320000116000010