Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SRI (vector, 16B)

Test 1: uops

Code:

  sri v0.16b, v1.16b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.012

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.012

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004208510131101210365076410361040208211000
1004208410131101210365076810341034208011000
1004208410131101210365024810001000208411000
1004208410131101210365078010361041208211000
1004208410131101210365078010361042209611000
1004208410131101210365078010361042208011000
1004211710131101210365078010361042208611000
1004208410131101210365078010361040208211000
1004208410131101210365078010361042208211000
1004208510131101210365082810421046208411000

Test 2: Latency 1->1

Code:

  sri v0.16b, v1.16b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020520066101111031000810210034300509248101002001000620020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020012110000100
1020420033101011011000010010000300509580101342001004820020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092471002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010

Test 3: Latency 1->2

Code:

  sri v0.16b, v0.16b, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000030005092481010020001000420020008110000100
1020420033101011011000010010000030005092481010020001000420020008110000100
1020420033101011011000010010000030005092481010020001000420020008110000100
1020420033101011011000010010000030005092481010020001000420020008110000100
1020420033101011011000010010000030005092481010020001000420020008110000100
1020420033101011011000010010000030005092481010020001000420020008110000100
1020420033101011011000010010000030005092481010020001000420020008110000100
1020420033101011011000010010000030005092481010020001000420020008110000100
1020420033101011011000010010000030005092481010020001000420020008110000100
1020420033101011011000010010000030005092481010020001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092481002020100042020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sri v0.16b, v8.16b, #3
  movi v1.16b, 0
  sri v1.16b, v8.16b, #3
  movi v2.16b, 0
  sri v2.16b, v8.16b, #3
  movi v3.16b, 0
  sri v3.16b, v8.16b, #3
  movi v4.16b, 0
  sri v4.16b, v8.16b, #3
  movi v5.16b, 0
  sri v5.16b, v8.16b, #3
  movi v6.16b, 0
  sri v6.16b, v8.16b, #3
  movi v7.16b, 0
  sri v7.16b, v8.16b, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
16020440525801101018000901008001330032005280112200800122001600241160000100
16020440108801101018000901008001330032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032019680148200800482001600241160000100
16020440086801091018000801008001230032005280112200800122001600261160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244385480020118000910800133032005280022208001220160026116000010
1600244131380011118000010800003032000080010208000020160000116000010
1600244041580011118000010800003032000080010208000020160000116000010
1600244041580011118000010800003032000080010208000020160000116000010
1600244041580011118000010800003032000080010208000020160000116000010
1600244041580011118000010800003032000080010208000020160000116000010
1600244045380011118000010800003032000080010208000020160000116000010
1600244038780011118000010800003032000080010208000020160000116000010
1600244039280011118000010800003032000080010208000020160000116000010
1600244039480011118000010800003032000080010208000020160000116000010

Test 5: throughput

Count: 16

Code:

  sri v0.16b, v16.16b, #3
  sri v1.16b, v16.16b, #3
  sri v2.16b, v16.16b, #3
  sri v3.16b, v16.16b, #3
  sri v4.16b, v16.16b, #3
  sri v5.16b, v16.16b, #3
  sri v6.16b, v16.16b, #3
  sri v7.16b, v16.16b, #3
  sri v8.16b, v16.16b, #3
  sri v9.16b, v16.16b, #3
  sri v10.16b, v16.16b, #3
  sri v11.16b, v16.16b, #3
  sri v12.16b, v16.16b, #3
  sri v13.16b, v16.16b, #3
  sri v14.16b, v16.16b, #3
  sri v15.16b, v16.16b, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602048008216010710116000601001600103006400361601082001600122003200241160000100
1602058006916014210116004101001600533006400361601082001600122003200241160000100
1602048003416010510116000401001600083006400361601082001600122003200281160000100
1602048003416010510116000401001600083006400361601082001600122003200241160000100
1602048003416010510116000401001600083006400361601082001600122003200241160000100
1602048003416010510116000401001600083006400361601082001600122003200241160000100
1602048003416010510116000401001600083006400361601082001600122003200241160000100
1602048003416010510116000401001600083006400361601082001600122003200241160000100
1602048003416010510116000401001600083006400361601082001600122003200241160000100
1602048003416010510116000401001600083006400361601082001600122003200241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024800931600171116000610160010306400361600182016001220320000116000010
160024800531600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306403561601042016011020320000116000010
160024800341600111116000010160000306401921600602016006020320000116000010
160024800341600111116000010160000306401961600612016005920320000116000010
160025800681600491116003810160050306400001600102016000020320000116000010
160024800341600111116000010160000306401561600522016004620320000116000010
160024800341600111116000010160000306401961600612016006120320000116000010
160024800341600111116000010160000306401561600522016004820320000116000010
160024800341600111116000010160000306402001600622016006220320000116000010