Icestorm: SRI (vector, 16B) measurements

Code:

  sri v0.16b, v1.16b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.012

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.012

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	2085	1013	1	1012	1036	50764	1036	1040	2082	1	1000
1004	2084	1013	1	1012	1036	50768	1034	1034	2080	1	1000
1004	2084	1013	1	1012	1036	50248	1000	1000	2084	1	1000
1004	2084	1013	1	1012	1036	50780	1036	1041	2082	1	1000
1004	2084	1013	1	1012	1036	50780	1036	1042	2096	1	1000
1004	2084	1013	1	1012	1036	50780	1036	1042	2080	1	1000
1004	2117	1013	1	1012	1036	50780	1036	1042	2086	1	1000
1004	2084	1013	1	1012	1036	50780	1036	1040	2082	1	1000
1004	2084	1013	1	1012	1036	50780	1036	1042	2082	1	1000
1004	2085	1013	1	1012	1036	50828	1042	1046	2084	1	1000

Test 2: Latency 1->1

Code:

  sri v0.16b, v1.16b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10205	20066	10111	103	10008	102	10034	300	509248	10100	200	10006	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20012	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509580	10134	200	10048	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	300	509248	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509247	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  sri v0.16b, v0.16b, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100
10204	20033	10101	101	10000	100	10000	0	300	0	509248	10100	200	0	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10004	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10
10024	20033	10021	21	10000	20	10000	70	509248	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sri v0.16b, v8.16b, #3
  movi v1.16b, 0
  sri v1.16b, v8.16b, #3
  movi v2.16b, 0
  sri v2.16b, v8.16b, #3
  movi v3.16b, 0
  sri v3.16b, v8.16b, #3
  movi v4.16b, 0
  sri v4.16b, v8.16b, #3
  movi v5.16b, 0
  sri v5.16b, v8.16b, #3
  movi v6.16b, 0
  sri v6.16b, v8.16b, #3
  movi v7.16b, 0
  sri v7.16b, v8.16b, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40525	80110	101	80009	0	100	80013	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40108	80110	101	80009	0	100	80013	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320196	80148	200	80048	200	160024	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	160026	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	0	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43854	80020	11	80009	10	80013	30	320052	80022	20	80012	20	160026	1	160000	10
160024	41313	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40415	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40415	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40415	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40415	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40453	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40387	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40392	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40394	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  sri v0.16b, v16.16b, #3
  sri v1.16b, v16.16b, #3
  sri v2.16b, v16.16b, #3
  sri v3.16b, v16.16b, #3
  sri v4.16b, v16.16b, #3
  sri v5.16b, v16.16b, #3
  sri v6.16b, v16.16b, #3
  sri v7.16b, v16.16b, #3
  sri v8.16b, v16.16b, #3
  sri v9.16b, v16.16b, #3
  sri v10.16b, v16.16b, #3
  sri v11.16b, v16.16b, #3
  sri v12.16b, v16.16b, #3
  sri v13.16b, v16.16b, #3
  sri v14.16b, v16.16b, #3
  sri v15.16b, v16.16b, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80082	160107	101	160006	0	100	160010	300	640036	160108	200	160012	200	320024	1	160000	100
160205	80069	160142	101	160041	0	100	160053	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320028	1	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80034	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80093	160017	11	160006	10	160010	30	640036	160018	20	160012	20	320000	1	160000	10
160024	80053	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640356	160104	20	160110	20	320000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640192	160060	20	160060	20	320000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640196	160061	20	160059	20	320000	1	160000	10
160025	80068	160049	11	160038	10	160050	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640156	160052	20	160046	20	320000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640196	160061	20	160061	20	320000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640156	160052	20	160048	20	320000	1	160000	10
160024	80034	160011	11	160000	10	160000	30	640200	160062	20	160062	20	320000	1	160000	10

SRI (vector, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations