Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SRI (vector, 8H)

Test 1: uops

Code:

  sri v0.8h, v1.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1004203310011100010005024810001000200011000
1005206610091100810345024810001000200011000

Test 2: Latency 1->1

Code:

  sri v0.8h, v1.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000620020008110000100
1020420033101011011000010010000300509248101002001000620020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10025200661002921100082010034705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010

Test 3: Latency 1->2

Code:

  sri v0.8h, v0.8h, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509580101342001004620020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100
1020420033101011011000010010000300509248101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024200331002121100002010000705092481002020100042020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010
10024200331002121100002010000705092481002020100002020000111000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sri v0.8h, v8.8h, #3
  movi v1.16b, 0
  sri v1.8h, v8.8h, #3
  movi v2.16b, 0
  sri v2.8h, v8.8h, #3
  movi v3.16b, 0
  sri v3.8h, v8.8h, #3
  movi v4.16b, 0
  sri v4.8h, v8.8h, #3
  movi v5.16b, 0
  sri v5.8h, v8.8h, #3
  movi v6.16b, 0
  sri v6.8h, v8.8h, #3
  movi v7.16b, 0
  sri v7.8h, v8.8h, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
16020440458801101018000901008001330032005280112200800122001600261160000100
16020440099801101018000901008001330032005680113200800132001600241160000100
16020440096801101018000901008001330032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440382801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100
16020440086801091018000801008001230032005280112200800122001600241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
16002443809800191180008010800123032000080010208000020160000116000010
16002441293800111180000010800003032000080010208000020160000116000010
16002440379800111180000010800003032000080010208000020160000116000010
16002440416800111180000010800003032019680058208004820160000116000010
16002440434800111180000010800003032000080010208000020160000116000010
16002440427800111180000010800003032000080010208000020160000116000010
16002440421800111180000010800003032000080010208000020160000116000010
16002440425800111180000010800003032000080010208000020160000116000010
16002440407800111180000010800003032000080010208000020160000116000010
16002440425800111180000010800003032000080010208000020160098116000010

Test 5: throughput

Count: 16

Code:

  sri v0.8h, v16.8h, #3
  sri v1.8h, v16.8h, #3
  sri v2.8h, v16.8h, #3
  sri v3.8h, v16.8h, #3
  sri v4.8h, v16.8h, #3
  sri v5.8h, v16.8h, #3
  sri v6.8h, v16.8h, #3
  sri v7.8h, v16.8h, #3
  sri v8.8h, v16.8h, #3
  sri v9.8h, v16.8h, #3
  sri v10.8h, v16.8h, #3
  sri v11.8h, v16.8h, #3
  sri v12.8h, v16.8h, #3
  sri v13.8h, v16.8h, #3
  sri v14.8h, v16.8h, #3
  sri v15.8h, v16.8h, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204801071601071011600061001600103006400361601082001600122003200281160000100
160204800441601051011600041001600083006400361601082001600122003200241160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100
160204800341601051011600041001600083006400441601102001600142003200281160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100
160204800341601051011600041001600083006402001601522001600602003200241160000100
160204800341601051011600041001600083006400361601082001600122003200281160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100
160204800341601051011600041001600083006400361601082001600122003200241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024806711600151116000410160008306400441600202016001420320000116000010
160024800541600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800391600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010
160024800341600111116000010160000306400001600102016000020320000116000010