Icestorm: SRSRA (vector, 16B) measurements

Code:

  srsra v0.16b, v1.16b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  srsra v0.16b, v1.16b, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	307	769247	10133	202	10046	200	20012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20010	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10025	30066	10027	21	10006	20	10031	70	768905	10020	20	10006	20	20090	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20008	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10006	20	20008	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  srsra v0.16b, v0.16b, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	769247	10051	20	10047	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	22	20084	12	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10025	30067	10027	21	10006	20	10032	70	768905	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  srsra v0.16b, v8.16b, #3
  movi v1.16b, 0
  srsra v1.16b, v8.16b, #3
  movi v2.16b, 0
  srsra v2.16b, v8.16b, #3
  movi v3.16b, 0
  srsra v3.16b, v8.16b, #3
  movi v4.16b, 0
  srsra v4.16b, v8.16b, #3
  movi v5.16b, 0
  srsra v5.16b, v8.16b, #3
  movi v6.16b, 0
  srsra v6.16b, v8.16b, #3
  movi v7.16b, 0
  srsra v7.16b, v8.16b, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	40713	80109	101	80008	0	100	80012	0	300	0	320052	80112	200	0	80012	200	0	160024	1	0	160000	100
160204	40117	80110	101	80009	0	100	80013	0	300	0	320052	80112	200	0	80012	200	0	160026	1	0	160000	100
160204	40086	80109	101	80008	0	100	80012	0	300	0	320052	80112	200	0	80012	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	0	100	80012	0	300	0	320052	80112	200	0	80012	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	0	100	80012	0	300	0	320052	80112	200	0	80012	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	0	100	80012	0	300	0	320052	80112	200	0	80012	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	0	100	80012	0	300	0	320200	80149	200	0	80049	200	0	160024	1	0	160000	100
160204	40105	80110	101	80009	0	100	80013	0	300	0	320052	80112	200	0	80012	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	0	100	80012	0	300	0	320052	80112	200	0	80012	200	0	160024	1	0	160000	100
160204	40086	80109	101	80008	0	100	80012	0	300	0	320052	80112	200	0	80012	200	0	160024	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	43840	80019	11	80008	0	10	80012	30	320052	80022	20	80012	20	0	160000	1	0	160000	10
160024	41271	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160024	40401	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160024	40419	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160024	40430	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160024	40418	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160024	40417	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160024	40398	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160024	40412	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	0	160000	1	0	160000	10
160024	40427	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	0	160092	1	0	160000	10

Test 5: throughput

Count: 16

Code:

  srsra v0.16b, v16.16b, #3
  srsra v1.16b, v16.16b, #3
  srsra v2.16b, v16.16b, #3
  srsra v3.16b, v16.16b, #3
  srsra v4.16b, v16.16b, #3
  srsra v5.16b, v16.16b, #3
  srsra v6.16b, v16.16b, #3
  srsra v7.16b, v16.16b, #3
  srsra v8.16b, v16.16b, #3
  srsra v9.16b, v16.16b, #3
  srsra v10.16b, v16.16b, #3
  srsra v11.16b, v16.16b, #3
  srsra v12.16b, v16.16b, #3
  srsra v13.16b, v16.16b, #3
  srsra v14.16b, v16.16b, #3
  srsra v15.16b, v16.16b, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	80055	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320028	1	0	160000	100
160204	80035	160107	101	160006	0	100	160010	300	640044	160110	200	160014	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640216	160156	200	160063	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	0	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80151	160015	11	160004	10	160008	30	640044	160020	20	160014	20	320000	1	160000	10
160024	80057	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320120	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	320000	1	160000	10

SRSRA (vector, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations