Icestorm: SRSRA (vector, 4S) measurements

Code:

  srsra v0.4s, v1.4s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  srsra v0.4s, v1.4s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20096	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10006	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	0	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  srsra v0.4s, v0.4s, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	202	20092	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	20008	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10004	20	20008	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  srsra v0.4s, v8.4s, #3
  movi v1.16b, 0
  srsra v1.4s, v8.4s, #3
  movi v2.16b, 0
  srsra v2.4s, v8.4s, #3
  movi v3.16b, 0
  srsra v3.4s, v8.4s, #3
  movi v4.16b, 0
  srsra v4.4s, v8.4s, #3
  movi v5.16b, 0
  srsra v5.4s, v8.4s, #3
  movi v6.16b, 0
  srsra v6.4s, v8.4s, #3
  movi v7.16b, 0
  srsra v7.4s, v8.4s, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5013

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40476	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160026	1	160000	100
160204	40124	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160026	1	160000	100
160204	40099	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160026	1	160000	100
160205	40138	80146	101	80045	100	80049	300	320056	80113	200	80013	200	160026	1	160000	100
160204	40103	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160026	1	160000	100
160204	40103	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160026	1	160000	100
160204	40103	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160026	1	160000	100
160204	40103	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160026	1	160000	100
160204	40103	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160026	1	160000	100
160204	40103	80110	101	80009	100	80013	300	320056	80113	200	80013	200	160026	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5051

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	44405	80074	11	80063	0	10	80067	30	320052	80022	20	80012	20	160072	1	160000	10
160024	41575	80084	11	80073	0	10	80073	30	320000	80010	20	80000	20	160142	1	160000	10
160024	44401	80083	11	80072	0	10	80072	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40388	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40428	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40373	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40434	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
290370	93900	148829	4193	141986	2650	4441	141990	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40457	80011	11	80000	0	10	80000	30	320204	80060	20	80050	20	160024	1	160000	10
160024	42288	80011	11	80000	0	10	80000	30	320000	80010	20	80000	20	160024	1	160000	10

Test 5: throughput

Count: 16

Code:

  srsra v0.4s, v16.4s, #3
  srsra v1.4s, v16.4s, #3
  srsra v2.4s, v16.4s, #3
  srsra v3.4s, v16.4s, #3
  srsra v4.4s, v16.4s, #3
  srsra v5.4s, v16.4s, #3
  srsra v6.4s, v16.4s, #3
  srsra v7.4s, v16.4s, #3
  srsra v8.4s, v16.4s, #3
  srsra v9.4s, v16.4s, #3
  srsra v10.4s, v16.4s, #3
  srsra v11.4s, v16.4s, #3
  srsra v12.4s, v16.4s, #3
  srsra v13.4s, v16.4s, #3
  srsra v14.4s, v16.4s, #3
  srsra v15.4s, v16.4s, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160204	80036	160105	101	160004	100	160008	300	640200	160152	200	160060	23413	14980	330495	10516	8047	165193	13061
160204	80041	160107	101	160006	100	160010	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640044	160110	200	160014	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	0	320024	1	0	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160024	80294	160015	11	160004	10	160008	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80054	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	30	640376	160109	20	160110	14227	9234	320222	6368	5120	160006	8252
160024	80096	160015	11	160004	10	160008	30	640200	160062	20	160062	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10
160024	80035	160011	11	160000	10	160000	30	640000	160010	20	160000	20	0	320000	1	0	160000	10

SRSRA (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations