Icestorm: SSRA (vector, 2S) measurements

Code:

  ssra v0.2s, v1.2s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	ldst uops in schedulers (5b)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)
1004	3033	1001	1	1000	0	0	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	0	0	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	0	0	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	0	0	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	0	0	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	0	0	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	0	0	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	0	0	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	0	0	1000	75905	1000	1000	2000	1	1000
1004	3033	1001	1	1000	0	0	1000	75905	1000	1000	2000	1	1000

Test 2: Latency 1->1

Code:

  ssra v0.2s, v1.2s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10006	200	20012	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10006	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 3: Latency 1->2

Code:

  ssra v0.2s, v0.2s, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10204	30033	10101	101	10000	100	10000	307	769232	10133	202	10047	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100
10204	30033	10101	101	10000	100	10000	300	768905	10100	200	10004	200	20008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	769273	10052	20	10044	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10
10024	30033	10021	21	10000	20	10000	70	768905	10020	20	10000	20	20000	11	10000	10

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ssra v0.2s, v8.2s, #3
  movi v1.16b, 0
  ssra v1.2s, v8.2s, #3
  movi v2.16b, 0
  ssra v2.2s, v8.2s, #3
  movi v3.16b, 0
  ssra v3.2s, v8.2s, #3
  movi v4.16b, 0
  ssra v4.2s, v8.2s, #3
  movi v5.16b, 0
  ssra v5.2s, v8.2s, #3
  movi v6.16b, 0
  ssra v6.2s, v8.2s, #3
  movi v7.16b, 0
  ssra v7.2s, v8.2s, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	40457	80110	101	80009	100	80013	300	320204	80150	200	80050	200	160024	1	160000	100
160205	40163	80144	101	80043	100	80047	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320052	80112	200	80012	200	160024	1	160000	100
160204	40086	80109	101	80008	100	80012	300	320056	80113	200	80013	200	160024	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5052

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	43746	80020	11	80009	10	80013	30	320052	80022	20	80012	20	160000	1	160000	10
160024	41230	80011	11	80000	10	80000	30	320196	80058	20	80048	20	160000	1	160000	10
160024	40419	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40415	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40418	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40418	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40404	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40401	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40411	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10
160024	40418	80011	11	80000	10	80000	30	320000	80010	20	80000	20	160000	1	160000	10

Test 5: throughput

Count: 16

Code:

  ssra v0.2s, v16.2s, #3
  ssra v1.2s, v16.2s, #3
  ssra v2.2s, v16.2s, #3
  ssra v3.2s, v16.2s, #3
  ssra v4.2s, v16.2s, #3
  ssra v5.2s, v16.2s, #3
  ssra v6.2s, v16.2s, #3
  ssra v7.2s, v16.2s, #3
  ssra v8.2s, v16.2s, #3
  ssra v9.2s, v16.2s, #3
  ssra v10.2s, v16.2s, #3
  ssra v11.2s, v16.2s, #3
  ssra v12.2s, v16.2s, #3
  ssra v13.2s, v16.2s, #3
  ssra v14.2s, v16.2s, #3
  ssra v15.2s, v16.2s, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160204	80083	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160107	101	160006	100	160010	300	640044	160110	200	160014	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320028	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640044	160110	200	160014	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320024	1	160000	100
160204	80035	160105	101	160004	100	160008	300	640036	160108	200	160012	200	320028	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? simd retires (ee)	? int retires (ef)
160024	80152	160015	11	160004	10	160008	0	30	0	640036	160018	20	0	160012	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640212	160065	20	0	160063	20	320000	1	160000	10
160024	80037	160011	11	160000	10	160000	0	30	0	640044	160020	20	0	160014	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10
160024	80035	160011	11	160000	10	160000	0	30	0	640000	160010	20	0	160000	20	320000	1	160000	10

SSRA (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations