Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SSRA (vector, 8H)

Test 1: uops

Code:

  ssra v0.8h, v1.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000
1004303310011100010007590510001000200011000

Test 2: Latency 1->1

Code:

  ssra v0.8h, v1.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000620020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000707689051002020100042020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000667692471005120100442020000111000010
10024300331002121100002010000707689051002020100002020092111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010

Test 3: Latency 1->2

Code:

  ssra v0.8h, v0.8h, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100
1020430033101011011000010010000300768905101002001000420020008110000100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0033

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
10024300331002121100002010000687692471005120100452020012111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707692321005120100452020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100002020000111000010
10024300331002121100002010000707689051002020100062020000111000010

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  ssra v0.8h, v8.8h, #3
  movi v1.16b, 0
  ssra v1.8h, v8.8h, #3
  movi v2.16b, 0
  ssra v2.8h, v8.8h, #3
  movi v3.16b, 0
  ssra v3.8h, v8.8h, #3
  movi v4.16b, 0
  ssra v4.8h, v8.8h, #3
  movi v5.16b, 0
  ssra v5.8h, v8.8h, #3
  movi v6.16b, 0
  ssra v6.8h, v8.8h, #3
  movi v7.16b, 0
  ssra v7.8h, v8.8h, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5011

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1602044045180110101800091008001330032005280112200800122001600241160000100
1602044011980109101800081008001230032005680113200800132001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602054013180147101800461008005030032005280112200800122001600241160000100
1602044008680109101800081008001230032005680113200800132001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100
1602044008680109101800081008001230032005280112200800122001600241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5053

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
1600244378080019118000810800123032005280022208001220160000116000010
1600244128580011118000010800003032000080010208000020160000116000010
1600244034880011118000010800003032000080010208000020160000116000010
1600244041680011118000010800003032000080010208000020160000116000010
1600244040680011118000010800003032000080010208000020160000116000010
1600244041780011118000010800003032000080010208000020160000116000010
1600244040880011118000010800003032000080010208000020160000116000010
1600244040880011118000010800003032000080010208000020160000116000010
1600244039780011118000010800003032000080010208000020160288116000010
1600244040480011118000010800003032000080010208000020160000116000010

Test 5: throughput

Count: 16

Code:

  ssra v0.8h, v16.8h, #3
  ssra v1.8h, v16.8h, #3
  ssra v2.8h, v16.8h, #3
  ssra v3.8h, v16.8h, #3
  ssra v4.8h, v16.8h, #3
  ssra v5.8h, v16.8h, #3
  ssra v6.8h, v16.8h, #3
  ssra v7.8h, v16.8h, #3
  ssra v8.8h, v16.8h, #3
  ssra v9.8h, v16.8h, #3
  ssra v10.8h, v16.8h, #3
  ssra v11.8h, v16.8h, #3
  ssra v12.8h, v16.8h, #3
  ssra v13.8h, v16.8h, #3
  ssra v14.8h, v16.8h, #3
  ssra v15.8h, v16.8h, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160204800551601051011600041001600083006400361601082001600122003200241160000100
160204800351601071011600061001600103026402081601562021600622003200281160000100
160204800351601051011600041001600083006400441601102001600142003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006402041601532001600612003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160205800701601431011600421001600543006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100
160204800351601051011600041001600083006400361601082001600122003200241160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)? int output thing (e9)? simd retires (ee)? int retires (ef)
160024802091600171116000610160010030064003616001820016001220320000116000010
160025800711600551116004410160056030064000016001020016000020320000116000010
160024800351600111116000010160000030064000016001020016000020320000116000010
160024800351600111116000010160000030064000016001020016000020320000116000010
160024800351600111116000010160000030064000016001020016000020320000116000010
160024800351600111116000010160000030064000016001020016000020320000116000010
160024800351600111116000010160000030064000016001020016000020320000116000010
160024800511600111116000010160000030064000016001020016000020320000116000010
160024800351600111116000010160000030064000016001020016000020320000116000010
160024800351600111116000010160000030064000016001020016000020320000116000010