Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ST1 (multiple, 1 reg, 4H)

Test 1: uops

Code:

  st1 { v0.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
61005294021003110021000400010001000200011000
61004291271001110001000400010001000200011000
61004291181001110001000400010001000200011000
61004291541001110001000400010001000200011000
61004294901001110001000400010001000200011000
61004297541001110001000400010001000200011000
61004296221001110001000400010001000200011000
61004291431001110001000400010001000200011000
61004291541001110001000400010001000200011000
61004291371001110001000400010001000200011000

Test 2: throughput

Count: 8

Code:

  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
802058014580119101800181008000130013599388010120080008202160100280000100
802048004480101101800001008000130013598508010120080008200160016180000100
802048003780101101800001008000130013598508010120080008200160016180000100
802048003780101101800001008000130013598508010120080008200160016180000100
802048003780101101800001008000130013598508010120080008200160016180000100
802048005280101101800001008000130013598688010120080008200160016180000100
802048003780101101800001008000130013598508010120080008200160016180000100
802048003780101101800001008000130013598508010120080008200160104180000100
802048004580101101800001008000130013598508010120080008200160016180000100
802048003780101101800001008000130013598508010120080008200160016180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
800258029480029118001810800013013599748001120800082016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800258007380028118001710800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016009818000010
800248005280011118000010800003013600078001020800002016000018000010
800248004580011118000010800003013600078001020800002016000018000010
800258007380028118001710800003013600078001020800002016000018000010