Icestorm: ST1 (multiple, 1 reg, 4H) measurements

Code:

  st1 { v0.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
61005	29402	1003	1	1002	1000	4000	1000	1000	2000	1	1000
61004	29127	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29118	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29154	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29490	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29754	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29622	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29143	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29154	1001	1	1000	1000	4000	1000	1000	2000	1	1000
61004	29137	1001	1	1000	1000	4000	1000	1000	2000	1	1000

Count: 8

Code:

  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]
  st1 { v0.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	80145	80119	101	80018	100	80001	300	1359938	80101	200	80008	202	160100	2	80000	100
80204	80044	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	100
80204	80052	80101	101	80000	100	80001	300	1359868	80101	200	80008	200	160016	1	80000	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160104	1	80000	100
80204	80045	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	100
80204	80037	80101	101	80000	100	80001	300	1359850	80101	200	80008	200	160016	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	80294	80029	11	80018	10	80001	30	1359974	80011	20	80008	20	160000	1	80000	10
80024	80045	80011	11	80000	10	80000	30	1360007	80010	20	80000	20	160000	1	80000	10
80025	80073	80028	11	80017	10	80000	30	1360007	80010	20	80000	20	160000	1	80000	10
80024	80045	80011	11	80000	10	80000	30	1360007	80010	20	80000	20	160000	1	80000	10
80024	80045	80011	11	80000	10	80000	30	1360007	80010	20	80000	20	160000	1	80000	10
80024	80045	80011	11	80000	10	80000	30	1360007	80010	20	80000	20	160000	1	80000	10
80024	80045	80011	11	80000	10	80000	30	1360007	80010	20	80000	20	160098	1	80000	10
80024	80052	80011	11	80000	10	80000	30	1360007	80010	20	80000	20	160000	1	80000	10
80024	80045	80011	11	80000	10	80000	30	1360007	80010	20	80000	20	160000	1	80000	10
80025	80073	80028	11	80017	10	80000	30	1360007	80010	20	80000	20	160000	1	80000	10

ST1 (multiple, 1 reg, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations